Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2723
20.6.27
RIRBCTL—Offset 5Ch
RIRB Control
Access Method
Default: 00h
Type:
Memory Mapped I/O Register
(Size: 8 bits)
RIRBCTL:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
RESE
RVED
0
RESPO
N
S
E
_OV
E
RRUN_INTERRUPT_CONTROL
RIRB_DMA_E
NABLE
RE
SP
ONSE
_INTERRU
PT
_C
ONTROL
Bit
Range
Default &
Access
Description
7:3
00h
RO
RESERVED0:
reserved
2
0h
RW
RESPONSE_OVERRUN_INTERRUPT_CONTROL:
If this bit is set and GIE and CIE are
enabled the hardware will generate an interrupt when the Response Overrun Interrupt
Status bit is set.
1
0h
RW
RIRB_DMA_ENABLE:
0 DMA Stop 1 DMA Run After SW writes a 0 to this bit the HW
may not stop immediately. The hardware will physically update the bit to a 0 when the
DMA engine is truly stopped. SW must read a 0 from this bit to verify that the DMA is
truly stopped.
0
0h
RW
RESPONSE_INTERRUPT_CONTROL:
0 Disable Interrupt 1 Generate an interrupt if
GIE and CIE are enabled after N number of Responses are sent to the RIRB buffer OR
when an empty Response slot is encountered on all SDI_x inputs whichever occurs first
. The N counter is reset when the interrupt is generated.