Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2724
Datasheet
20.6.28
RIRBSTS—Offset 5Dh
RIRB Status
Access Method
Default: 00h
Type:
Memory Mapped I/O Register
(Size: 8 bits)
RIRBSTS:
AZLBAR Type:
PCI Configuration Register (Size: 32 bits)
AZLBAR Reference:
[B:0, D:27, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
RESE
RVED
0
RE
SPONSE
_OVE
RRUN
_
INTE
RRUP
T
_ST
A
T
U
S
RESE
RVED
1
RES
P
O
N
SE_INTE
RRUP
T
Bit
Range
Default &
Access
Description
7:3
00h
RO
RESERVED0:
reserved
2
0h
RW
RESPONSE_OVERRUN_INTERRUPT_STATUS:
Hardware sets this bit to a 1 when the
RIRB DMA engine is not able to write the incoming responses to memory before
additional incoming responses overrun the internal FIFO. When the overrun occurs the
hardware will drop the responses which overrun the buffer. An interrupt may be
generated if the Response Overrun Interrupt Control bit is set. Note that this status bit
is set even if an interrupt is not enabled for this event. Software clears this flag by
writing a 1 to this bit.
1
0h
RO
RESERVED1:
reserved
0
0h
RW
RESPONSE_INTERRUPT:
Hardware sets this bit to a 1 when an interrupt has been
generated after N number of Responses are sent to the RIRB buffer OR when an empty
Response slot is encountered on all SDI x inputs whichever occurs first . Note that this
status bit is set even if an interrupt is not enabled for this event. Software clears this
flag by writing a 1 to this bit.