Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
2806
Datasheet
21.5.4
SSP Clocking
SSP could be used as either clock masters or clock slaves. Consequently, theses IP
have dual clock domains.
have dual clock domains.
The first clock domain is clocked from an internal clock (e.g., fabric clock) and is used
for generic logic like interrupt generation and register access.
for generic logic like interrupt generation and register access.
The second clock domain drives the serial shift register (either driven internally or
externally). When driven internally, this clock can be sourced from XTAL clock 25 MHz
or PLL 19.2 MHz. These clocks are then divided down within the serial interface IP to
generate the final bit clock for the interface.
externally). When driven internally, this clock can be sourced from XTAL clock 25 MHz
or PLL 19.2 MHz. These clocks are then divided down within the serial interface IP to
generate the final bit clock for the interface.
After power on, if the SSP input IO clock is in high state, first transition of the clock
from high to low may be missing due to the Soc clock gating logic.
from high to low may be missing due to the Soc clock gating logic.
Note:
“Frame Master” mode cannot be used when operating as clock slave and “Frame Slave”
mode cannot be used when operating as clock master.
mode cannot be used when operating as clock master.
21.5.5
M/N Divider
LPE SSP in master mode uses the SSP CCLK to drive the serial clock. It has very limited
option to divide CCLK. An M/N divider is added between the 19.2/25 MHz clock (XOSC)
from CCU to each SSP CCLK input as shown in following diagram:
option to divide CCLK. An M/N divider is added between the 19.2/25 MHz clock (XOSC)
from CCU to each SSP CCLK input as shown in following diagram:
Note:
The maximum SSP CCLK frequency is listed in Table 132.
Figure 110.SSP CCLK Structure
SSP0
M/N
XOSC = 25MHz
/ PLL = 19.2MHz
CFG REG
SSP1
M/N
CFG REG
SSP2
M/N
CFG REG
SSP2 CCLK
SSP1 CCLK
SSP0 CCLK