Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Low Power Engine (LPE) for Audio (I
2
S)
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2813
Note:
The I2Sx_FRM Delay must not extend beyond the end of T4. I2Sx_FRM Width must be
asserted for at least 1 I2Sx_CLK, and should be de-asserted before the end of the T4
cycle (for example, in terms of time, not bit values, (T5 + T6) <= (T1 + T2 + T3 + T4),
1<= T6 < (T2 + T3 + T4), and (T5 + T6) >= (T1 + 1) to ensure that I2Sx_FRM is
asserted for at least 2 edges of the I2Sx_CLK). The T1 Start Delay value should be
programmed to 0 when the I2Sx_CLK is enabled by either of the SSCR1.ECRA or
SSCR1.ECRB bits. While the PSP can be programmed to generate the assertion of
I2Sx_FRM during the middle of the data transfer (after the MSB was sent), the
Enhanced SSP will not be able to receive data in Frame slave mode (SSCR1SFRMDIR =
1) if the assertion of Frame is not before the MSB is sent (i.e. T5 <= T2 if
SSCR1.SFRMDIR =1). Transmit Data will transition from the “End of Transfer Data
State” to the next MSB value upon the assertion of Frame. The Start Delay field should
be programmed to 0 whenever I2Sx_CLK or I2Sx_FRM is configured as an input. Clock
state is not defined between two active frame periods. Clock can be active or inactive
between two active frame periods.
asserted for at least 1 I2Sx_CLK, and should be de-asserted before the end of the T4
cycle (for example, in terms of time, not bit values, (T5 + T6) <= (T1 + T2 + T3 + T4),
1<= T6 < (T2 + T3 + T4), and (T5 + T6) >= (T1 + 1) to ensure that I2Sx_FRM is
asserted for at least 2 edges of the I2Sx_CLK). The T1 Start Delay value should be
programmed to 0 when the I2Sx_CLK is enabled by either of the SSCR1.ECRA or
SSCR1.ECRB bits. While the PSP can be programmed to generate the assertion of
I2Sx_FRM during the middle of the data transfer (after the MSB was sent), the
Enhanced SSP will not be able to receive data in Frame slave mode (SSCR1SFRMDIR =
1) if the assertion of Frame is not before the MSB is sent (i.e. T5 <= T2 if
SSCR1.SFRMDIR =1). Transmit Data will transition from the “End of Transfer Data
State” to the next MSB value upon the assertion of Frame. The Start Delay field should
be programmed to 0 whenever I2Sx_CLK or I2Sx_FRM is configured as an input. Clock
state is not defined between two active frame periods. Clock can be active or inactive
between two active frame periods.
21.7
Programming Model
The CPU or DMA access data through the Enhanced SSP Port’s Transmit and Receive
FIFOs. A CPU access takes the form of programmed I/O, transferring one FIFO entry
per access. CPU accesses would normally be triggered off of an SSSR Interrupt and
FIFOs. A CPU access takes the form of programmed I/O, transferring one FIFO entry
per access. CPU accesses would normally be triggered off of an SSSR Interrupt and
Table 228. Programmable Protocol Parameters
Symbol
Definition
(Register.Bit Field)
Range
Units
Serial Clock Mode
(SSPSP.SCMODE)
(Drive, Sample, I2Sx_CLK
Idle)
0 = Fall, Rise, Low
1 = Rise, Fall, Low
1 = Rise, Fall, Low
2 = Rise, Fall, High
3 = Fall, Rise, High
3 = Fall, Rise, High
Serial Frame Polarity
(SSPSP.SFRMP)
High or Low
T1
Start Delay
(SSPSP.STRTDLY)
0–7
Clock Period
T2
Dummy Start
(SSPSP.DMYSTRT)
0–3
Clock Period
T3
Data Size
(SSCRO.EDSS AND SSCRO.DSS)
4–32
Clock Period
T4
Dummy Stop
(SSPSP.DMYSTOP)
0–3
Clock Period
T5
I2Sx_FRM Delay
(SPSP.SFRMDLY)
0–88
Half Clock
Period
T6
I2Sx_FRM Width
(SSPSP.SFRMWDTH)
1–44
Clock Period
End of Transfer Data State
(SSPSP.ETDS)
Low or [bit 0]