Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2851
21.11.16 reg_CLKCTL_type (CLKCTL)—Offset 78h
LPE Clock Control Register
Access Method
Default: 0000000000070013h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LP
E
_
S
C
_
B
U
S
Y
SC
_
LPE
_DO
N
E
LP
E_
SC
_
M
SG
Bit
Range
Default &
Access
Description
63
0b
RW
LPE_SC_BUSY:
Busy. When this bit is cleared, the SC CPU is Ready to accept a new
message
62
0b
RW
SC_LPE_DONE:
Done. When the bit is set, the SC CPU completed operation and
requests attention from LPE
61:0
0h
RW
LPE_SC_MSG:
LPE to SC CPU Message
Type:
Memory Mapped I/O Register
(Size: 64 bits)
CLKCTL:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1
RS
VD
0
R
SVD
RS
VD
1
E
N
_S
S
P2_C
LK
E
N
_S
S
P1_C
LK
E
N
_S
S
P0_C
LK
RS
VD
2
OS
C
_
MO
D
E
FR
CH
NG
GO
FR
C
H
NG
AC
K
RS
VD
3
CL
K
_
D
IV
Bit
Range
Default &
Access
Description
63:32
0b
RO
RSVD0:
Reserved
31:25
0000000b
RO
RSVD:
Reserved
24:19
0b
RO
RSVD1:
Reserved
18
1b
RW
EN_SSP2_CLK:
clock output enable
17
1b
RW
EN_SSP1_CLK:
clock output enable
16
1b
RW
EN_SSP0_CLK:
clock output enable