Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2856
Datasheet
21.11.23 reg_IPCPSH_type (IPCPSH)—Offset B0h
The Inter-process Status and Message register for PSH contains a message sent from
the PSH CPU to LPE. The format of the CPU message bits (29:0) is not defined in the
HW specs. It is defined in the LPE Firmware specifications. The message may contain
optional data fields stored in the shared memory region (mailbox). When the message
is written in this register, the software must set bit 63 to indicate that the IPCPSH is not
empty. Setting Busy also asserts interrupt request to LPE if the interrupt is enabled in
the IMRLPEPSH. After LPE reads the message code from the register, it must perform a
write with bit 63 cleared. The PSH CPU must not attempt to write into IPCIA if bit 63 is
set.
Access Method
Default: 0000000000000000h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
PS
H_L
PE_
IPC_
R
equ
est
_
M
ask
PSH_
LP
E_I
PC_Do
ne
_M
ask
Bit
Range
Default &
Access
Description
63:2
0b
RO
RSVD0:
Reserved
1
0b
RW
PSH_LPE_IPC_Request_Mask:
IPCPSH interrupt Enable to LPE
0
0b
RW
PSH_LPE_IPC_Done_Mask:
IPCLPEPSH interrupt Enable to LPE
Type:
Memory Mapped I/O Register
(Size: 64 bits)
IPCPSH:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PS
H_L
PE_
B
U
SY
LP
E
_
PS
H_DON
E
PSH_
LP
E_M
S
G
Bit
Range
Default &
Access
Description
63
0b
RW
PSH_LPE_BUSY:
Busy. When this bit is cleared, the LPE Ready to accept a message