Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2880
Datasheet
Default: 00000000h
21.12.19 SSP Control 5 Register (SSCR5)—Offset 78h
Software should only program this register if configuring the SSP in I2S/LJ mode or
PCM master mode with the Tangier fixes. If neither is being enabled, SW can leave this
register at the default power on value.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
0
TO
T
_
FR
M
_
PR
D
RSVD
Bit
Range
Default &
Access
Description
31:16
0b
RO
RSVD0:
Reserved
15:7
000h
RW
Total Frame Period (TOT_FRM_PRD):
The total frame period (both asserted and de-
asserted time of frame), measured in bit clocks, that is driven in I2S, LJ and PCM
master modes. This can be controlled to get the desired accuracy on frame rate. A value
of 0 and a value smaller than the value programmed in SSCR5.FrameAssertedWidth are
illegal
6:0
00h
RO
Reserved (RSVD):
Reserved.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
SSCR5:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:21, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
FRM_A
S
R
T
_W
ID
T
H
RS
VD
Bit
Range
Default &
Access
Description
31:26
0b
RO
RSVD0:
Reserved
25:1
0000000h
RW
Frame Assert Width (FRM_ASRT_WIDTH):
This field controls the width of the
asserted period of frame in I2S, LJ and PCM master modes. A value of 1 indicates a
width of 2 bit clock period, 2 indicates a width of 3 bit clock periods, etc. The frame
width is Frame Assert Width + 1.