Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
430
Datasheet
14.9.15
MSAC—Offset 60h
This register determines the size of the graphics memory aperture. Only the system
BIOS will write this register based on pre- boot address allocation efforts. Graphics may
read this register to determine the correct aperture size. System BIOS needs to save
this value on boot so that it can reset it correctly during S3 resume. SOXi Context
Save/Restore : Yes. The size of the aperture must not be modified by software after its
location is written into GMADR (offset 18h).
Access Method
Default: 00020000h
14.9.16
BGSM—Offset 70h
Base of GTT table in Gfx Stolen Memory SOXi Context Save/Restore : Yes. Note : IVB
located this register in device 0, 0xB4. Mirrored into Device 2. The GTT table is located
within Graphics Stolen Memory in DRAM space. The base of stolen memory will always
be below 4G.
Access Method
Bit
Range
Default &
Access
Description
31:20
000h
RW/L
BDSM (BDSM_0):
BDSM: BASE_OF_Data_STOLEN_MEMORY. This register contains
bits 31 to 20 of the base address of Data stolen DRAM memory. For certain GTLC
generated accesses, this base register will be added to the GTLC provided offset
address, forming the full physical address for the PFI fabric. This is also used as a base
for VGA paged accesses. The display engine also uses the register. Signal :
gvd_dsp_cfg_BSM_zcznfwh[31:20].
19:1
00000h
RO
RSVD (RSVD_1):
Reserved
0
0b
RW/L
BDSM_LOCK (BDSM_LOCK_2):
This bit will lock all writeable settings in this register,
including itself.
Type:
PCI Configuration Register
(Size: 32 bits)
Power Well:
Core
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD_0
LHS
A
S_1
RS
VD_2
Bit
Range
Default &
Access
Description
31:19
0000h
RO
RSVD (RSVD_0):
Reserved
18:17
01b
RW
LHSAS (LHSAS_1):
Untrusted Aperture Size (LHSAS): 00 : bits [28:27] of GMADR
register are made R/W allowing 128MB of GMADR. 01 : bit [28] of GMADR is made R/W
and bit [27] of GMADR is forced to zero allowing 256MB of GMADR. 10 : Illegal
programming. 11: bits [28:27] of GMADR register are made Read only and forced to
zero, allowing only 512MB of GMADR.
16:0
00000h
RO
RSVD (RSVD_2):
Reserved