Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

432

Datasheet

Message Signaled Interrupts Capability ID.SOXi Context Save/Restore : Yes. Message 

Signaled Control Register. SOXi Context Save/Restore : Yes

31:20

000h

RO

Reserved. This field is used to set the base of Protected Content 

Memory. This corresponds to bits 31:20 of the system memory address range, giving a 

1MB granularity. This value MUST be at least 1MB above the base and below the top of 

stolen memory. This register is locked (becomes read-only) when PAVPLOCK = 1b.

19:18

00b

RO

Reserved. Note : IVB provided 256KB granularity, so these 2 bits 

were RW to support that size option. However, VV will only support 1MB so Gunit will tie 

bits 19:18 to '00'.

17:6

000h

RO

Reserved

5

0b

RO

0b ? 1MB Note : IVB had this as a RW bit with value '1' 

indicating size 256KB support. Since VV only supports 1MB size, this register is RO for 

VV. These are the only sizes supported for IVB. The IVB is going to run PAVP3 Mode 

Serpent applications using per-App selection. Therefore, the size chosen should always 

be 1MB configuration even if Lite mode is chosen using PAVPC register (bit_3 = 0) for 

PAVP2 Mode Applications. This is because CB^2 code needs to be always loaded, since 

an App. Which opts for per-App Serpent mode will also execute the CB^2 code). The 

driver may consider it a BIOS programming error, if PAVPC Serpent Mode is selected 

with only 256KB of WOPCM size. However PAVPC Lite Mode with 1M WOPCM size is 

acceptable and not an error, as this may involve per-App selected Serpent Mode.

4

0b

RW/L

Override of Unsolicited Connection State Attack and 

Terminate. 0b Disable Override. Attack Terminate allowed. 1b Enable Override. Attack 

Terminate disallowed. This register bit is locked (becomes read-only) when PAVPLOCK = 

1b

3

0b

RW/L

In IVB, this bit is a care only for PAVP2 mode of 

operation (and a chicken bit is also set). For IVB PAVP2 mode: 0 : Lite Mode (Non-

Serpent Mode) 1: Serpent Mode For PAVP3 mode of operation, this bit_3 is a care, only 

if the per-App Memory Config is disabled due to the clearing of an additional Chicken 

bit_9 in IVB Crypto Function Control_1 Reg (@ address 0x320F0h). For chicken bit 

enabled IVB PAVP3 mode, this one type boot time programming has been replaced by 

per-Media App. Programming (through the Media Crypto Copy command). Note that IVB 

PAVP2 or PAVP3 Mode selection is done by programming bit_8 of MFX_MODE ? Video 

Mode Register. (Note again, that when in PAVP3 Mode, the per-App Memory Config. 

(Serpent/Lite) feature for enabling, requires the further setting of a global one time 

chicken bit to be set (bit_9 = ?1/mask_bit_25 = ?1) in the IVB Crypto Function 

Control_1 Register @ address 0x320F0h). Note : Valleyview does not support PAVP2 

mode. Only PAVP3 mode is supported (a superset of PAVP2).

2

0b

RW/L

This bit will lock all writeable contents in this register 

when set(including itself).Only a hw reset can unlock the register again. This Lock bit if 

PAVP is enabled (PAVPE = 1)

1

0b

RW/L

0: PAVP functionality is disabled. 1: enabled. This register is 

locked when PAVPLOCK=1

0

0b

RW/L

PCME = Protected Content Memory Enable This field enables 

Protected Content Memory within Graphics Stolen Memory. This memory is the same as 

the WOPCM area. The size of the WOPCM area is defined by bit_5 of this register. 

WOPCM is the only remaining flavor of range protected memory. 0: WOPCM protection 

disabled. 1 : WOPCM protection enabled. This bit must be programmed to 1 when PAVP 

is enabled. With per-App Memory configuration support in IVB, the range check for the 

WOPCM memory area should always happen when this bit is set, irrespective of Lite or 

AES mode programming, or PAVP2 or PAVP3 Mode programming.