Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

480

Datasheet

30

0b

RW

[DevVLVP] 

0 = Disable DPLLA clock from being driven out 

1 = Enable DPLLA clock to be drive out 

[DevCDV] Reserved 

DPLLA Serial DVO High Speed IO clock Enable 

0 = High Speed IO Clock Disabled (default) 

1 = High Speed IO Clock Enabled (must be set in Serial DVO and HDMI modes)

29

0b

RW

[DevCDV, DevVLVP]:  

Indicate the reference clock of PLL A is enable 

0 Disable (default) 

1 Enable

28

0b

RW

When in native VGA modes, writes to the VGA MSR register 

causes the value in the selected (by MSR bits) VGA clock control register to be loaded 

into the active register. This allows the VGA clock select to select the pixel frequency 

between the two standard VGA pixel frequencies. 

0 = VGA MSR(3:2) Clock Control bits select DPLL A Frequency 

1 = Disable VGA Control

27:26

0b

RW

[DevVLVP] When two 

pipes are enabled for eDP and both pipes can run with the same DP frequency either 

162MHz or 270MHz. Setting this mode can allow using only DPLLA to feed both pipes. 

DPLLB should be shutdown to save power. This control is double buffered. 

00 = Disabled 

01 = Enabled 

10 = Reserved 

11 = Reserved 

[DevCDV] Reserved 

DPLLA Mode Select : Configure the DPLLA for various supported Display Modes 

00 = Reserved 

01 = DPLLA in DAC/Serial DVO/UDI/Integrated TV mode 

10 = DPLLA in LVDS mode (Mobile devices ONLY) otherwise RESERVED 

11 = DP

25:24

0b

RW

[DevCDV, DevVLVP] 

FPA0/FPA1 P2 Clock Divide: 

00 = Divide by 10. This is used when Dot Clock =( 270MHz in sDVO, HDMI, or DAC 

modes 

01 = Divide by 5. This is used when Dot Clock )270MHz 

10 = Reserved 

11 = Reserved 

For DPLLA in LVDS mode, BITS(27:26)=10 

00 = Divide by 14. This is used in Single-Channel LVDS 

01 = Divide by 7. This is used in Dual-Channel LVDS 

10 = Reserved 

11 = Reserved

23:16

0b

RW

[DevCDV, DevVLVP] 

FPA0/ FPA1 P1 Post Divisor: Writes to this byte cause the staging register contents to be 

written into the active register when in the VGA mode of operation. This will also occur 

when the VGA MSR register is written.  

00000001b = Divide by one 

00000010b = Divide by two 

00000100b = Divide by three 

00001000b = Divide by four 

00010000b = Divide by five 

00100000b = Divide by six 

01000000b = Divide by seven 

10000000b = Divide by Eight 

All other values are illegal and should not be used

15

0b

RW

Write as zero 

PLLA Lock [DevCDV, DevVLVP] (RO) 

1 - PLLA Lock  

0 PLLA unlock

14

0b

RW

[DevVLVP] This control selects the VCC voltage in DPLL 

0 = 1.0 V (default) 

1 = voltage for LDO circuit (for TNG use) 

[DevCDV] Reserved