Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
482
Datasheet
Default: 00006000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
DPLL_B_VCO_E
N
ABLE
DPLLB_E
XTE
R
NAL_CL
OCK_BUFFER_E
N
ABLE
REFB_CL
O
CK_E
NABLE
VG
A_MOD
E
_DIS
ABLE
ENABL
E
_SING
LE_DP
LLB_FRE
QUENC
Y
_FOR
_
B
O
T
H_P
IP
E
S
RE
SE
RVED
RESE
RVE
D
_1
RESE
RVE
D
_2
DPIO_COMMON_REGIST
ER_INTE
R
FA
C
E
_C
LO
CK_SE
LECT_CRIC
LK
SEL
DPLL_B_REFE
RENCE_INP
U
T_S
E
LE
CT
RESE
RVE
D
_3
DIS
PL
A
Y
_
R
A
T
E
_
S
W
IT
C
H_
P
IPE
B
RESE
RVE
D
_4
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
DPLL_B_VCO_ENABLE:
Disabling the PLLB will cause the display dot clock to stop.
0 = DPLLB is disabled in its lowest power state (default)
1 = DPLLB is enabled and operational (42usec until lock without calibration and 110usec
for calibration)
30
0b
RW
DPLLB_EXTERNAL_CLOCK_BUFFER_ENABLE:
[DevVLVP]
0 = Disable DPLLB clock from being driven out
1 = Enable DPLLB clock to be drive out
[DevCDV] Reserved
DPLLB Serial DVO High Speed IO clock Enable
0 = High Speed IO Clock Disabled (default)
1 = High Speed IO Clock Enabled (must be set in Serial DVO and HDMI modes)
29
0b
RW
REFB_CLOCK_ENABLE:
[DevCDV, DevVLVP]:
Indicate the reference clock of PLL A is enable
0 Disable (default)
1 Enable
28
0b
RW
VGA_MODE_DISABLE:
When in native VGA modes, writes to the VGA MSR register
causes the value in the selected (by MSR bits) VGA clock control register to be loaded
into the active register. This allows the VGA clock select to select the pixel frequency
between the two standard VGA pixel frequencies.
0 = VGA MSR(3:2) Clock Control bits select DPLL A Frequency
1 = Disable VGA Control