Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

481

DPLL B Control Registers DPLL B Control (cpdmmreg.v reg04_lt)

13

1b

RW

[DevVLVP] This control selects the integrated 

core refclk or external OSC refclk as the input clock source to DPLL A. 

0 = External refclk pad (27MHz) 

1 = Integrated core refclk (default is 100 MHz) 

[DevCDV] Reserved 

PLL Reference Input Select: The PLL reference should be selected based on the display 

device that is being driven. The standard reference clock is used for CRT modes using 

the analog display port or LCD panels for both the sDVO connected transmitter or the 

integrated LVDS. TV Clock in should be selected when driving an sDVO connected TV 

encoder.

12:9

0b

RW

[DevCDV, DevVLVP] 

Parallel to Serial Load Pulse phase selection: Programmable select bits to choose the 

relative phase of the high speed (10X) DPLL clock used for generating the parallel to 

serial load pulse for digital display port on PCIe. The relative phase is the number of flop 

delays (phase 0 represents 1 flop delay) of the 1X parallel data synchronization signal in 

the 10X clock domain. 

The earliest selectable clock phase is 4. A phase selection of 10 or greater simply 

extends the flop delay count to sample delayed data. 

0100 = use clock phase-4 

0101 = use clock phase-5 

0110 = use clock phase-6 (Default value) 

0111 = use clock phase-7 

1000 = use clock phase-8 

1001 = use clock phase-9 

1010 = use clock phase-10 

1011 = use clock phase-11 

1100 = use clock phase-12 

1101 = use clock phase-13 

Phases 0 through 3 are not available for Load Pulse selection. 

[DevCL] The following programming is recommended for Crestline based on PV timing 

analysis: 

1101 use clock phase-13 

[DevBLC, DevCTG] Reserved. Programming for load pulse is in PXP AFE config space.

8

0b

RW

[DevCTG, DevCDV, DevVLVP] 

Switching this bit (transition 0 to 1 or 1 to 0) causes the DSP HW to disable and than 

enable the DPLL during vblank (2 row) in order to switch the frequency at the DPLL 

(new dividers stored at the DPIO which is double buffered) 

(This bit is only available when bits 17:16 of the PIPEACONF register are 00) 

[DevBW, DevCL, DevBLC] Reserved

7:0

0b

RO

[DevVLVP] This field contains the two 4-bit ModPhy 

lane status. One for PortB and one for PortC 

Bit 7:4 = Port C PhyStatus[3:0] 

Bit 3:0 = Port B PhyStatus[3:0] 

[DevBW, DevCL, DevBLC, DevCDV] Reserved 

[DevCTG] FPA1 P1 Post Divisor: Writes to this byte cause the staging register contents 

to be written into the active register when in the VGA mode of operation. This will also 

occur when the VGA MSR register is written.  

00000001b - Divide by one 

00000010b - Divide by two 

00000100b - Divide by three 

00001000b - Divide by four 

00010000b - Divide by five 

00100000b - Divide by six 

01000000b - Divide by seven 

10000000b - Divide by Eight 

All other values are illegal and should not be used 

AccessType: Read Only