Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

483

27:26

0b

RW

[DevVLVP] When two 

pipes are enabled for eDP and both pipes can run with the same DP frequency either 

162MHz or 270MHz. Setting this mode can allow using only DPLLB to feed both pipes. 

DPLLA should be shutdown to save power.  

00 = Disabled 

01 = Enabled 

10 = Reserved 

11 = Reserved 

[DevCDV] Reserved 

DPLLB Mode Select : Configure the DPLLB for various supported Display Modes 

00 = Reserved 

01 = DPLLA in DAC/Serial DVO/UDI/Integrated TV mode 

10 = DPLLA in LVDS mode (Mobile devices ONLY) otherwise RESERVED 

11 = DP

25:24

0b

RW

[DevCDV, DevVLVP] 

FPB0/FPB1 P2 Clock Divide: 

00 = Divide by 10. This is used when Dot Clock =( 270MHz in sDVO, HDMI, or DAC 

modes 

01 = Divide by 5. This is used when Dot Clock )270MHz 

10 = Reserved 

11 = Reserved 

For DPLLB in LVDS mode, BITS(27:26)=10 

00 = Divide by 14. This is used in Single-Channel LVDS 

01 = Divide by 7. This is used in Dual-Channel LVDS 

10 = Reserved 

11 = Reserved

23:16

0b

RW

[DevCDV, DevVLVP] 

FPB0/ FPB1 P1 Post Divisor: Writes to this byte cause the staging register contents to be 

written into the active register when in the VGA mode of operation. This will also occur 

when the VGA MSR register is written.  

00000001b = Divide by one 

00000010b = Divide by two 

00000100b = Divide by three 

00001000b = Divide by four 

00010000b = Divide by five 

00100000b = Divide by six 

01000000b = Divide by seven 

10000000b = Divide by Eight 

All other values are illegal and should not be used

15

0b

RW

Write as zero 

PLLB Lock [DevCDV, DevVLVP] (RO) 

1 - PLLB Lock  

0 PLLB unlock

14

1b

RW

[DevVLVP] This bit is to control the clock source for DPIO Common Register Interface 

0 = Use external reclk pad 

1 = Use integrated core refclk (default)

13

1b

RW

[DevVLVP] This control selects the integrated 

core refclk or external OSC refclk as the input clock source to DPLL B. 

0 = External refclk pad (27MHz) 

1 = Integrated core refclk (default is 100 MHz) 

[DevCDV] Reserved 

PLL Reference Input Select: The PLL reference should be selected based on the display 

device that is being driven. The standard reference clock is used for CRT modes using 

the analog display port or LCD panels for both the sDVO connected transmitter or the 

integrated LVDS. TV Clock in should be selected when driving an sDVO connected TV 

encoder.