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Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
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Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
494
Datasheet
19
0b
RW
SPRITE_D_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
18
0b
RW
CURSOR_A_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
17
0b
RW
CURSOR_B_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
16
0b
RW
DISPLAY_BLENDER_A_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating 
controlled by unit enabling logic 
1 = Disable clock gating function
15
0b
RW
DISPLAY_BLENDER_B_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating 
controlled by unit enabling logic 
1 = Disable clock gating function
14
0b
RW
DISPLAY_GAMMA_CORRECTION_A_PSR_CLOCK_GATING_DISABLE: 
0 = Clock 
gating controlled by unit enabling logic 
1 = Disable clock gating function
13
0b
RW
DISPLAY_GAMMA_CORRECTION_B_PSR_CLOCK_GATING_DISABLE: 
0 = Clock 
gating controlled by unit enabling logic 
1 = Disable clock gating function
12
0b
RW
DISPLAY_GCI_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
11
0b
RW
AUDFUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function(default)
10
0b
RW
AUDBUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
9
1b
RW
CPDUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function (default)
8
0b
RW
DDBMUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
7
0b
RW
DPFUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
6
0b
RW
DPIOUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
5
0b
RW
DISPLAYPORT_DPTUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating 
controlled by unit enabling logic 
1 = Disable clock gating function
4
0b
RW
DPOUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
3
0b
RW
HDCPUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
2
0b
RW
VRDUNIT_PSR_CLOCK_GATING_DISABLE: 
0 = Clock gating controlled by unit 
enabling logic 
1 = Disable clock gating function
Bit 
Range
Default & 
Access
Field Name (ID): Description