Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
496
Datasheet
29
0b
RW
CURSOR_DATA_BUFFER_RAM_CLOCK_GATING_DISABLE:
0 = Enable RAM bank
clock gating function (default)
1 = Disable RAM bank clock gating function
28
0b
RW
AUDM_UNIT_RAM_CLOCK_GATING_DISABLE:
[DevCTG, DevCDV]
[DeBLC] Reserved.
[DevCL] WIZ Z coeff readback return FIFO Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
27
0b
RW
RESERVED_1:
[DevCDV]
[DevCTG] DPFC Unit RAM Clock Gating Disable:
[DevBLC] Reserved.
[DevCL] Display Data Buffer2 (Overlay) Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
26
0b
RW
DISPLAY_DATA_BUFFER1_RAM_CLOCK_GATING_DISABLE:
0 = Enable RAM
bank clock gating function (default)
1 = Disable RAM bank clock gating function
25
0b
RW
HDCP_UNIT_RAM_CLOCK_GATING_DISABLE:
[DevBLC, DevCTG, DevCDV]
[DevCL] ME RAM Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
24
0b
RW
DPTUNIT_RAM_CLOCK_GATING_DISABLE:
[DevVLVP]
[DevCTG, DevCDV] DPIOM Unit RAM Clock Gating Disable:
[DevBLC] Reserved.
[DevCL] WIZ polygon FIFO RAM Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
23
0b
RW
RESERVED_2:
[DevCDV]
[DevBLC] and [DevCTG] Reserved.
[DevCL] VF RAM Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
22
0b
RW
RESERVED_3:
[DevCDV]
[DevBLC] and [DevCTG] Reserved.
[DevCL] SF RAMClock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
21
0b
RW
RESERVED_4:
[DevCDV]
[DevBLC] and [DevCTG] Reserved.
[DevCL] WMIZ Latency FIFO Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
20
0b
RW
RESERVED_5:
[DevCDV]
[DevBLC] and [DevCTG] Reserved.
[DevCL] TC FIFO Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
19
0b
RW
RESERVED_6:
[DevBLC, DevCTG, DevCDV]
[DevCL] SV FIFO Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
18
0b
RW
RESERVED_7:
[DevCDV]
[DevBLC] and [DevCTG] BD Unit RAM Clock Gating Disable:
[DevCL] Latency FIFO Clock Gating Disable:
0 = Enable RAM bank clock gating function (default)
1 = Disable RAM bank clock gating function
Bit
Range
Default &
Access
Field Name (ID): Description