Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
697
14.11.42 PIPEA_PP_OFF_DELAYS—Offset 6120Ch
PipeA Panel Power off Sequencing Delays ([DevCL, DevCTG, DevCDV]) PP Delay Off
values (dplrreg.v DPLRppoff_sd)
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31:30
0b
RW
PANEL_CONTROL_PORT_SELECT:
These bits define to which port the embedded
panel is connected. This is used for automatic control of the panel power. If the selected
port is disabled or if the port is not on pipe-B, then, the power sequence will not allow a
panel power up.
00 = Reserved
01 = Panel is connected to the embedded DisplayPort B
10 = Panel is connected to the embedded DisplayPort C
11 = Reserved
The selection of non-existent ports are not allowed. This programming will disable panel
power sequencing logic.
29
0b
RW
RESERVED:
Reserved.
28:16
0b
RW
POWER_UP_DELAY:
Programmable value of panel power sequencing delay during
panel power up. This provides the time delay for the T1+T2 time sequence. The time
unit used is the 100us timer.
15:13
0b
RW
RESERVED_1:
Reserved.
12:0
0b
RW
POWER_ON_TO_BACKLIGHT_ENABLE_DELAY:
Programmable value of panel power
sequencing delay during panel power up. This provides the time delay for the T5 (T3 for
DisplayPort) time sequence. The time unit used is the 100us timer.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h