Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

696

Datasheet

PipeA Panel Power on Sequencing Delays ([DevCL, DevCTG, DevCDV]) PP On Delay 

values (dplrreg.v DPLRppon_sd)

Default: 00000000h

1

0b

RW

Enabling this bit causes the panel to power down when a 

reset warning comes to the GMCH from the ICH. When system reset is initiated, the 

embedded panel port automatically begins the panel power down sequence. If the panel 

is not on during a reset event, this bit is ignored. 

0 = Do not run panel power down sequence when reset is detected 

1 = Run panel power down sequence when system is reset

0

0b

RW

Writing this bit can occur any time, it will only be used at 

the completion of any current power cycle. 

0 = The panel power state target is off, if the panel is either on or in a power on 

sequence, a power off sequence is started as soon as the panel reaches the power on 

state. This may include a power cycle delay. If the panel is currently off, there is no 

change of the power state or sequencing done. 

1= The panel power state target is on, if the panel is in either the off state or a power 

off sequence, if all pre-conditions are met, a power on sequence is started as soon as 

the panel reaches the power off state. This may include a power cycle delay. If the panel 

is currently off, there is no change of the power state or sequencing done. While the 

panel is on or in a power on sequence, the register write lock will be enabled.

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 

bits)
GTTMMADR_LSB Reference: 

[B:0, D:2, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PA

NEL_CONTROL

_

P

O

R

T

_SELECT

RE

SERV

ED

PO

WE

R_UP_

D

E

LA

Y

RE

SE

RVED

_

1

POWER_ON_T

O

_

B

A

CKLIGHT_E

N

ABLE

_

D

ELA

Y