Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1782
Datasheet
16.6.18
Timeout Control Register (TIMEOUT_CTL)—Offset 2Eh
At the initialization of the Host Controller, the Host Driver shall set the Data Timeout
Counter Value according to the Capabilities register.
Access Method
Default: 00h
7:6
0h
RO
Upper Bits of SDCLK Frequency Select (upper_sdclk_freq_sel):
Host Controller
Versions 1.00 and 2.00 do not support these bits and they are treated as 00b fixed
value (ROC).
Host Controller Version 3.00 shall support these bits to expand SDCLK Frequency Select
to 10-bit. Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK Frequency Select.
5:3
0h
RO
Rsvd (rsvd):
Reserved.
2
0b
RW
SD Clock Enable (sd_clk_en):
The Host Controller shall stop SDCLK when writing this
bit to 0. SDCLK Frequency Select can be changed when this bit is 0. Then, the Host
Controller shall maintain the same clock frequency until SDCLK is stopped (Stop at
SDCLK=0). If the Card Inserted in the Present State register is cleared, this bit shall be
cleared.
•
•
1 = Enable
•
0 = Disable
1
0b
RO
Internal Clock Stable (int_clk_stable):
This bit is set to 1 when SD clock is stable
after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait
to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a
clock oscillator that requires setup time.
•
•
1 = Ready
•
0 = Not Ready
0
0b
RW
Internal Clock Enable (int_clk_en):
This bit is set to 0 when the Host Driver is not
using the Host Controller, or when the Host Controller awaits a wakeup event. The Host
Controller should stop its internal clock to go to a very low power state. Still, registers
shall be able to be read and written. Clock starts to oscillate when this bit is set to 1.
When clock oscillation is stable, the Host Controller shall set Internal Clock Stable in this
register to 1. This bit shall not affect card detection.
•
•
1 = Oscillate
•
0 = Stop
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
re
se
rv
ed
data_time
out_cn
t_v
al