Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

2178

Datasheet

9

0b

RW

When set to 1, and HCHalted (HCH) = 1, then the 

xHC shall perform a Restore State operation and restore its internal state. When set to 1 

and Run/Stop (R/S) = 1 or HCHalted (HCH) = 0, or when cleared to 0, no Restore State 

operation shall be performed. This flag always returns 0 when read. Refer to the Restore 

 (RSS) flag in the USBSTS register for information on Restore State 

completion. Refer to the xHCI for USB specification, for more information. Note that 

undefined behavior may occur if a Restore State operation is initiated while Save State 

 (SSS) = 1.  

When this register is exposed by a Virtual Function (VF), this bit only controls restoring 

the state of the xHC instance presented by the selected VF. Refer to the xHCI for USB 

specification for more information.

Core

8

0b

RW

When written by software with 1 and HCHalted (HCH) = 

1, then the xHC shall save any internal state that may be restored by asubsequent 

Restore State operation. When written by software with 1 and HCHalted (HCH) =0, or 

written with 0, no Save State operation shall be performed. This flag always returns 0 

when read. Refer to the Save State Status (SSS) flag in the USBSTS register for 

information on Save State completion. Refer to the xHCI for USB specification for more 

information on xHC Save/Restore operation. Note that undefined behavior may occur if 

a Save State operation is initiated while Restore State Status (RSS) = 1.  

When this register is exposed by a Virtual Function (VF), this bit only controls saving the 

state of the xHC instance presented by the selected VF. Refer to the xHCI for USB 

specification for more information.

Core

7

0b

RW

Optional normative. If the Light HC Reset 

 (LHRC) bit in the HCCPARAMS register is 1, then this flag allows the driver to 

reset the xHC without affecting the state of the ports.  

A system software read of this bit as 0 indicates the Light Host Controller Reset has 

completed and it is safe for software to re-initialize the xHC. A software read of this bit 

as a 1 indicates the Light Host Controller Reset has not yet completed.  

If not implemented, a read of this flag shall always return a 0.  

All registers in the Aux Power well shall maintain the values that had been asserted prior 

to the Light Host Controller Reset. (Refer to the xHCI for USB specification for more 

information.)  

When this register is exposed by a Virtual Function (VF), this bit only generates a Light 

Reset to the xHC instance presented by the selected VF, e.g. disabling the VF's device 

slots and setting the associated VF Run bit to Stopped. Refer to the xHCI for USB 

specification for more information.

Core

6:4

0h

RO

Reserved.

Core

3

0b

RW

When this bit is a 1, and the HSE bit in the 

USBSTS register is a 1, the xHC shall assert out-of-band error signaling to the host. The 

signaling is acknowledged by software clearing the HSE bit. Refer to the xHCI for USB 

specification for more information.  

When this register is exposed by a Virtual Function (VF), the effect of the assertion of 

this bit on the Physical Function (PF0) is determined by the VMM. Refer to the xHCI for 

USB specification for more information.

Core