Renesas rl78 User Manual
RL78/G1A
CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00
199
Jul 04, 2013
Figure 6-10. Format of Timer Clock Select register m (TPSm) (1/2)
Address: F01B6H, F01B7H (TPS0) After reset: 0000H R/W
Symbol 15
14
13
12
11
10
9 8 7 6 5 4 3 2 1 0
TPSm 0
0
PRS
m31
PRS
m30
0 0
PRS
m21
PRS
m20
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
Selection of operation clock (CKmk)
Note
(k = 0, 1)
PRS
mk3
PRS
mk2
PRS
mk1
PRS
mk0
f
CLK
= 2 MHz
f
CLK
= 5 MHz f
CLK
= 10 MHz f
CLK
= 20 MHz f
CLK
= 32 MHz
0 0 0 0
f
CLK
2 MHz
5 MHz
10 MHz
20 MHz
32 MHz
0 0 0 1
f
CLK
/2
1 MHz
2.5 MHz
5 MHz
10 MHz
16 MHz
0 0 1 0
f
CLK
/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
8 MHz
0 0 1 1
f
CLK
/2
3
250 kHz
625 kHz
1.25 MHz
2.5 MHz
4 MHz
0 1 0 0
f
CLK
/2
4
125 kHz
313 kHz
625 kHz
1.25 MHz
2 MHz
0 1 0 1
f
CLK
/2
5
62.5 kHz
156 kHz
313 kHz
625 kHz
1 MHz
0 1 1 0
f
CLK
/2
6
31.3 kHz
78.1 kHz
156 kHz
313 kHz
500 kHz
0 1 1 1
f
CLK
/2
7
15.6 kHz
39.1 kHz
78.1 kHz
156 kHz
250 kHz
1 0 0 0
f
CLK
/2
8
7.81 kHz
19.5 kHz
39.1 kHz
78.1 kHz
125 kHz
1 0 0 1
f
CLK
/2
9
3.91 kHz
9.77 kHz
19.5 kHz
39.1 kHz
62.5 kHz
1 0 1 0
f
CLK
/2
10
1.95 kHz
4.88 kHz
9.77 kHz
19.5 kHz
31.3 kHz
1 0 1 1
f
CLK
/2
11
977 Hz
2.44 kHz
4.88 kHz
9.77 kHz
15.6 kHz
1 1 0 0
f
CLK
/2
12
488 Hz
1.22 kHz
2.44 kHz
4.88 kHz
7.81 kHz
1 1 0 1
f
CLK
/2
13
244 Hz
610 Hz
1.22 kHz
2.44 kHz
3.91 kHz
1 1 1 0
f
CLK
/2
14
122 Hz
305 Hz
610 Hz
1.22 kHz
1.95 kHz
1 1 1 1
f
CLK
/2
15
61.0 Hz
153 Hz
305 Hz
610 Hz
977 Hz
Note
When changing the clock selected for f
CLK
(by changing the system clock control register (CKC) value), stop
timer array unit (TTm = 00FFH).
Cautions 1. Be sure to clear bits 15, 14, 11, 10 to “0”.
2.
If
f
CLK
(undivided) is selected as the operation clock (CKmk) and TDRnm is set to 0000H (n = 0
or 1, m = 0 to 7), interrupt requests output from timer array units cannot be used.
Remarks 1. f
CLK
: CPU/peripheral hardware clock frequency
2.
Waveform of the clock to be selected in the TPSm register which becomes high level for one period
of f
CLK
from its rising edge (m = 1 to 15). For details, see 6.5.1 Count clock (f
TCLK
).
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