Renesas rl78 User Manual
RL78/G1A
CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00
200
Jul 04, 2013
Figure 6-10. Format of Timer Clock Select register m (TPSm) (2/2)
Address: F01B6H, F01B7H (TPS0) After reset: 0000H R/W
Symbol 15
14
13
12
11
10
9 8 7 6 5 4 3 2 1 0
TPSm 0
0
PRS
m31
PRS
m30
0 0
PRS
m21
PRS
m20
PRS
m13
PRS
m12
PRS
m11
PRS
m10
PRS
m03
PRS
m02
PRS
m01
PRS
m00
Selection of operation clock (CKm2)
ote
PRS
m21
PRS
m20
f
CLK
= 2 MHz
f
CLK
= 5 MHz f
CLK
= 10 MHz f
CLK
= 20 MHz f
CLK
= 32 MHz
0 0
f
CLK
/2
1 MHz
2.5 MHz
5 MHz
10 MHz
16 MHz
0 1
f
CLK
/2
2
500 kHz
1.25 MHz
2.5 MHz
5 MHz
8 MHz
1 0
f
CLK
/2
4
125 kHz
313 kHz
625 MHz
1.25 MHz
2 MHz
1 1
f
CLK
/2
6
31.3 kHz
78.1 kHz
156 kHz
313 kHz
500 kHz
Selection of operation clock (CKm3)
Note
PRS
m31
PRS
m30
f
CLK
= 2 MHz
f
CLK
= 5 MHz f
CLK
= 10 MHz f
CLK
= 20 MHz f
CLK
= 32 MHz
0 0
f
CLK
/2
8
7.81 kHz
19.5 kHz
39.1 kHz
78.1 kHz
125 kHz
0 1
f
CLK
/2
10
1.95 kHz
4.88 kHz
9.77 kHz
19.5 kHz
31.3 kHz
1 0
f
CLK
/2
12
488 Hz
1.22 kHz
2.44 kHz
4.88 kHz
7.81 kHz
1 1
f
CLK
/2
14
122 Hz
305 Hz
610 Hz
1.22 kHz
1.95 kHz
Note
When changing the clock selected for f
CLK
(by changing the system clock control register (CKC) value), stop
timer array unit (TTm = 00FFH).
The timer array unit must also be stopped if the operating clock (f
MCK
) or the valid edge of the signal input
from the TImn pin is selected.
Caution Be sure to clear bits 15, 14, 11, 10 to “0”.
By using channels 1 and 3 in the 8-bit timer mode and specifying CKm2 or CKm3 as the operation clock, the
interval times shown in Table 6-4 can be achieved by using the interval timer function.
Table 6-4. Interval Times Available for Operation Clock CKSm2 or CKSm3
Interval time
Note
(f
CLK
= 32 MHz)
Clock
10
μs 100 μs
1 ms
10 ms
f
CLK
/2
√
−
−
−
f
CLK
/2
2
√
−
−
−
f
CLK
/2
4
√
√
−
−
CKm2
f
CLK
/2
6
√
√
−
−
f
CLK
/2
8
−
√
√
−
f
CLK
/2
10
−
√
√
−
f
CLK
/2
12
−
−
√
√
CKm3
f
CLK
/2
14
−
−
√
√
Note The margin is within 5 %.
Remarks 1. f
CLK
: CPU/peripheral hardware clock frequency
2.
For details of asignal of f
CLK
/2
j
selected with the TPSm register, see 6.5.1 Count clock (f
TCLK
).