Renesas rl78 User Manual
RL78/G1A
CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00
350
Jul 04, 2013
Table 11-3. A/D Conversion Time Selection (1/4)
(1) 12-bit resolution mode (ADTYP = 0) When there is no stabilization wait time
(software trigger mode/hardware trigger no-wait mode)
Conversion Time Selection
A/D Converter Mode Register 0
(ADM0)
AV
DD
= 1.6 to 3.6 V AV
DD
= 1.6 to 3.6 V AV
DD
= 1.8 to 3.6 V AV
DD
= 2.4 to 3.6 V AV
DD
= 2.7 to 3.6 V
FR2 FR1 FR0 LV1 LV0
Mode Conversion
Clock (f
AD
)
Number of
Conversion
Clock
Conversion
Time
f
CLK
= 1 MHz f
CLK
= 4 MHz f
CLK
= 8 MHz f
CLK
= 16 MHz f
CLK
= 32 MHz
0 0 0
f
CLK
/32 1728/f
CLK
Setting
prohibited
54
μs
Note
0 0 1
f
CLK
/16 864/f
CLK
Setting
prohibited
54
μs
Note
27
μs
Note
0 1 0
f
CLK
/8 432/f
CLK
54
μs
Note
27
μs
Note
13.5
μs
Note
0 1 1
f
CLK
/6 324/f
CLK
40.5
μs
Note
20.25
μs
Note
10.125
μs
Note
1 0 0
f
CLK
/5 270/f
CLK
Setting
prohibited
33.75
μs
Note
16.875
μs
Note
8.4375
μs
Note
1 0 1
f
CLK
/4 216/f
CLK
54
μs
Note
27
μs
Note
13.5
μs
Note
6.75
μs
Note
1 1 0
f
CLK
/2 108/f
CLK
Setting
prohibited
27
μs
Note
13.5
μs
Note
6.75
μs
Note
3.375
μs
Note
1 1 1
0 0
Normal
1
f
CLK
/1
54 f
AD
(number
of
sampling
clock:
11 f
AD
)
54/f
CLK
54
μs
Note
13.5
μs
Note
6.75
μs
Note
3.375
μs
Note
Setting
prohibited
0 0 0
f
CLK
/32 2112/f
CLK
Setting
prohibited
66
μs
0 0 1
f
CLK
/16 1056/f
CLK
Setting
prohibited
66
μs 33
μs
0 1 0
f
CLK
/8 528/f
CLK
66
μs
Note
33
μs 16.5
μs
0 1 1
f
CLK
/6 396/f
CLK
49.5
μs
Note
24.75
μs 12.375
μs
1 0 0
f
CLK
/5 330/f
CLK
Setting
prohibited
41.25
μs
Note
20.625
μs
10.3125
μs
1 0 1
f
CLK
/4 264/f
CLK
66
μs
Note
33
μs
Note
16.5
μs 8.25
μs
1 1 0
f
CLK
/2 132/f
CLK
Setting
prohibited
33
μs
Note
16.5
μs
Note
8.25
μs 4.125
μs
1 1 1
0 1
Normal
2
f
CLK
/1
66 f
AD
(number
of
sampling
clock:
23 f
AD
)
66/f
CLK
66
μs
Note
16.5
μs
Note
8.25
μs
Note
4.125
μs Setting
prohibited
0 0 0
f
CLK
/32 2432/f
CLK
Setting
prohibited
76
μs
0 0 1
f
CLK
/16 1216/f
CLK
Setting
prohibited
76
μs 38
μs
0 1 0
f
CLK
/8 608/f
CLK
76
μs 38
μs 19
μs
0 1 1
f
CLK
/6 456/f
CLK
57
μs 28.5
μs 14.25
μs
1 0 0
f
CLK
/5 380/f
CLK
Setting
prohibited
47.5
μs 23.75
μs 11.875
μs
1 0 1
f
CLK
/4 304/f
CLK
76
μs
Note
38
μs 19
μs 9.5
μs
1 1 0
f
CLK
/2 152/f
CLK
Setting
prohibited
38
μs
Note
19
μs 9.5
μs 4.75
μs
1 1 1
1 0 Low-
voltage 1
f
CLK
/1
76 f
AD
(number
of
sampling
clock:
33 f
AD
)
76/f
CLK
76
μs
Note
19
μs
Note
9.5
μs 4.75
μs Setting
prohibited
0 0 0
f
CLK
/32 7360/f
CLK
Setting
prohibited
230
μs
0 0 1
f
CLK
/16 3680/f
CLK
Setting
prohibited
230
μs 115
μs
0 1 0
f
CLK
/8 1840/f
CLK
230
μs 115
μs 57.5
μs
0 1 1
f
CLK
/6 1380/f
CLK
172.5
μs 86.25
μs 43.125
μs
1 0 0
f
CLK
/5 1150/f
CLK
Setting
prohibited
143.75
μs 71.875
μs
35.9375
μs
1 0 1
f
CLK
/4 920/f
CLK
230
μs 115
μs 57.5
μs 28.75
μs
1 1 0
f
CLK
/2 460/f
CLK
Setting
prohibited
115
μs 57.5
μs 28.75
μs 14.375
μs
1 1 1
1 1 Low-
voltage 2
f
CLK
/1
230 f
AD
(number
of
sampling
clock:
187 f
AD
)
230/f
CLK
230
μs 57.5
μs 28.75
μs 14.375
μs
Setting
prohibited
Note When using ANI16 to ANI30, setting this value is prohibited.
(Cautions and Remark are listed on the next page.)
<R>