Renesas rl78 User Manual
RL78/G1A
CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00
352
Jul 04, 2013
Table 11-3. A/D Conversion Time Selection (2/4)
(2) 12-bit resolution mode (ADTYP = 0) When there is A/D power supply stabilization wait time
(hardware trigger wait mode (except second and subsequent conversion in sequential conversion mode and conversion of
channel specified by scan 1, 2, and 3 in scan mode
Note 1
))
A/D Power Supply Stabilization Wait Time + Conversion Time
Selection
A/D Converter Mode Register
0 (ADM0)
AV
DD
= 1.6 to 3.6 V AV
DD
= 1.6 to 3.6 V AV
DD
= 1.8 to 3.6 V AV
DD
= 2.4 to 3.6 V AV
DD
= 2.7 to 3.6 V
FR2 FR1 FR0 LV1 LV0
Mode
Conversion
Clock (f
AD
)
Number of
A/D Power
Supply
Stabilization
Wait Clock
Number of
Conversion
Clock
A/D Power
Supply
Stabilization
Wait Time
+Conversion
Time
f
CLK
= 1 MHz
f
CLK
= 4 MHz
f
CLK
= 8 MHz f
CLK
= 16 MHz f
CLK
= 32 MHz
0 0 0
f
CLK
/32 1732/f
CLK
Setting
prohibited
54.125
μs
Note 2
0 0 1
f
CLK
/16 868/f
CLK
Setting
prohibited
54.25
μs
Note 2
27.125
μs
Note 2
0 1 0
f
CLK
/8 436/f
CLK
54.5
μs
Note 2
27.25
μs
Note 2
13.625
μs
Note 2
0 1 1
f
CLK
/6 328/f
CLK
41
μs
Note 2
20.5
μs
Note 2
10.25
μs
Note 2
1 0 0
f
CLK
/5 274/f
CLK
Setting
prohibited
34.25
μs
Note 2
17.125
μs
Note 2
8.5625
μs
Note 2
1 0 1
f
CLK
/4 220/f
CLK
55
μs
Note 2
27.5
μs
Note 2
13.75
μs
Note 2
6.875
μs
Note 2
1 1 0
f
CLK
/2
4 f
CLK
112/f
CLK
Setting
prohibited
28
μs
Note 2
14
μs
Note 2
7
μs
Note 2
3.5
μs
Note 2
1 1 1
0 0
Normal
1
f
CLK
/1 2
f
CLK
54 f
AD
(number
of
sampling
clock:
11 f
AD
)
56/f
CLK
56
μs
Note 2
14
μs
Note 2
7
μs
Note 2
3.5
μs
Note 2
Setting
prohibited
0 0 0
f
CLK
/32 2170/f
CLK
Setting
prohibited
67.8125
μs
0 0 1
f
CLK
/16 1114/f
CLK
Setting
prohibited
69.625
μs 34.8125 μs
0 1 0
f
CLK
/8 586/f
CLK
73.25
μs
Note 2
36.625
μs 18.3125 μs
0 1 1
f
CLK
/6 454/f
CLK
56.75
μs
Note 2
28.375
μs 14.1875 μs
1 0 0
f
CLK
/5 388/f
CLK
Setting
prohibited
48.5
μs
Note 2
24.25
μs 12.125
μs
1 0 1
f
CLK
/4 322/f
CLK
80.5
μs
Note 2
40.25
μs
Note 2
20.125
μs 10.0625 μs
1 1 0
f
CLK
/2
58 f
CLK
190/f
CLK
Setting
prohibited
47.5
μs
Note 2
23.75
μs
Note 2
11.875
μs 5.9375 μs
1 1 1
0 1
Normal
2
f
CLK
/1 29
f
CLK
66 f
AD
(number
of
sampling
clock:
23 f
AD
)
95/f
CLK
95
μs
Note 2
23.75
μs
Note 2
11.875
μs
Note 2
5.9375
μs Setting
prohibited
0 0 0
f
CLK
/32 2447/f
CLK
Setting
prohibited
76.46875
μ s
Note 2
0 0 1
f
CLK
/16 1231/f
CLK
Setting
prohibited
76.9375
μs
Note 2
38.46875
μs
Note 2
0 1 0
f
CLK
/8 623/f
CLK
77.875
μs 38.9375 μs
Note 2
19.46875
μs
Note 2
0 1 1
f
CLK
/6 471/f
CLK
58.875
μs 29.4375 μs
Note 2
14.71875
μs
Note 2
1 0 0
f
CLK
/5 395/f
CLK
Setting
prohibited
49.375
μs 24.6875 μs
Note 2
12.34375
μs
Note 2
1 0 1
f
CLK
/4 319/f
CLK
79.75
μs
Note 2
39.875
μs 19.9375 μs
Note 2
9.96875
μs
Note 2
1 1 0
f
CLK
/2 167/f
CLK
Setting
prohibited
41.75
μs
Note 2
20.875
μs 10.4375 μs
Note 2
5.21875
μs
Note 2
1 1 1
1 0 Low-
voltage 1
f
CLK
/1
15 f
CLK
76 f
AD
(number
of
sampling
clock:
33 f
AD
)
91/f
CLK
91
μs
Note 2
22.75
μs
Note 2
11.375
μs 5.6875 μs
Note
Setting
prohibited
0 0 0
f
CLK
/32 7368/f
CLK
Setting
prohibited
230.25
μs
Note 2
0 0 1
f
CLK
/16 3688/f
CLK
Setting
prohibited
230.5
μs
Note 2
115.25
μs
Note 2
0 1 0
f
CLK
/8 1848/f
CLK
231
μs
Note 2
115.5
μs
Note 2
57.75
μs
Note 2
0 1 1
f
CLK
/6 1388/f
CLK
173.5
μs
Note 2
86.75
μs
Note 2
43.375
μs
Note 2
1 0 0
f
CLK
/5 1158/f
CLK
Setting
prohibited
144.75
μs
Note 2
72.375
μs
Note 2
36.1875
μs
Note 2
1 0 1
f
CLK
/4 928/f
CLK
232
μs
116
μs
Note 2
58
μs
Note 2
29
μs
Note 2
1 1 0
f
CLK
/2 468/f
CLK
Setting
prohibited
117
μs
58.5
μs
Note 2
29.25
μs
Note 2
14.625
μs
Note 2
1 1 1
1 1 Low-
voltage 2
f
CLK
/1
8 f
CLK
230 f
AD
(number
of
sampling
clock:
187 f
AD
)
238/f
CLK
238
μs 59.5
μs
29.75
μs
Note 2
14.875
μs
Note 2
Setting
prohibited
(Notes, Cautions and Remark are listed on the next page.)
<R>