Renesas rl78 User Manual

 

RL78/G1A 

 

CHAPTER  12   SERIAL  ARRAY  UNIT 

R01UH0305EJ0200  Rev.2.00 

 

 

515  

Jul 04, 2013 

UART reception is an operation wherein the RL78 microcontroller asynchronously receives data from another device 

(start-stop synchronization). 

For UART reception, the odd-number channel of the two channels used for UART is used.  The SMR register of both the 

odd- and even-numbered channels must be set. 

 

UART UART0 

UART1 

UART2 

Target channel 

Channel 1 of SAU0 

Channel 3 of SAU0 

Channel 1 of SAU1 

Pins 

used 

RxD0 RxD1 RxD2 

INTSR0 INTSR1 INTSR2 

Interrupt 

Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) 

Error 

interrupt 

INTSRE0 INTSRE1 INTSRE2 

Error detection flag 

•  Framing error detection flag (FEFmn) 
•  Parity error detection flag (PEFmn) 
•  Overrun error detection flag (OVFmn) 

Transfer data length 

7, 8 or 9 bits

 

Transfer rate

 Max. 

f

MCK

/6 [bps] (SDRmn[15:9] = 2 or more), Min. f

CLK

/(2 

× 2

15

 

× 128) [bps]  

Data phase 

Non-reverse output (default: high level) 

Reverse output (default: low level) 

Parity bit 

The following selectable 
•  No parity bit (no parity check) 
•  No parity judgment (0 parity) 
• Appending even parity 
•  Appending odd parity 

Stop bit 

1 bit addition 

Data direction 

MSB or LSB first 

Notes 1.  Only following UART0 can be specified for the 8-bit data length. 

 

2.  Use this operation within a range that satisfies the conditions above and the peripheral functions 

characteristics in the electrical specifications (see CHAPTER 29  ELECTRICAL SPECIFICATIONS (T

−40 to +85°C), CHAPTER 30  ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS T

−40 to +105°C)). 

 

Remarks 1.  f

MCK

: Operation clock frequency of target channel 

 

 

f

CLK

:  System clock frequency 

 

2.  m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11 

 

 

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