Renesas rl78 User Manual

 

RL78/G1A 

CHAPTER  14   MULTIPLIER  AND  DIVIDER/MULTIPLY-ACCUMULATOR 

 

• Initial setting 

<1>  Set the multiplication/division control register (MDUC) to 80H. 

<2>  Set the dividend (higher 16 bits) to multiplication/division data register A (H) (MDAH). 

<3>  Set the dividend (lower 16 bits) to multiplication/division data register A (L) (MDAL). 

<4>  Set the divisor (higher 16 bits) to multiplication/division data register B (H) (MDBH). 

<5>  Set the divisor (lower 16 bits) to multiplication/division data register B (L) (MDBL). 

<6>  Set bit 0 (DIVST) of the MDUC register to 1. 

 

(There is no preference in the order of executing steps <2> to <5>.) 

•  During operation processing 

<7>  The operation will end when one of the following processing is completed. 

•  A wait of at least 16 clocks (The operation will end when 16 clocks have been issued.) 

•  A check whether the DIVST bit has been cleared 

 (The read values of the MDBL, MDBH, MDCL, and MDCH registers during operation processing are not 

guaranteed.) 

• Operation end 

<8>  The DIVST bit is cleared and the operation ends.  At this time, an interrupt request signal (INTMD) is generated 

if the operation was performed with MACMODE = 0. 

<9>  Read the quotient (lower 16 bits) from the MDAL register. 

<10> Read the quotient (higher 16 bits) from the MDAH register. 

<11> Read the remainder (lower 16 bits) from multiplication/division data register C (L) (MDCL). 

<12> Read the remainder (higher 16 bits) from multiplication/division data register C (H) (MDCH). 

 

(There is no preference in the order of executing steps <9> to <12>.) 

• Next operation 

<13> Start with the initial settings of each step to change the operation mode.  When the same operation mode is 

used sequentially, settings <1> to <5> can be omitted. 

 

Remark  Steps <1> to <12> correspond to <1> to <12> in Figure 14-10. 

 

 

R01UH0305EJ0200  Rev.2.00 

 

 

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Jul 04, 2013