Renesas rl78 User Manual
RL78/G1A
CHAPTER 29 ELECTRICAL SPECIFICATIONS (T
A
=
−40 to +85°C)
R01UH0305EJ0200 Rev.2.00
882
Jul 04, 2013
(7) Communication at different potential (2.5 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(T
A
=
−40 to +85°C, 2.7 V ≤ EV
DD0
≤ V
DD
≤ 3.6 V, V
SS
= EV
SS0
= 0 V)
HS
Note 1
LS
Note 2
LV
Note 3
Parameter Symbol
Conditions
MIN.
MAX.
MIN.
MAX. MIN. MAX.
Unit
SCKp cycle time
t
KCY1
2.7 V
≤ EV
DD0
≤ 3.6 V,
2.3 V
≤ V
b
≤ 2.7 V,
C
b
= 20 pF, R
b
= 2.7 k
Ω
t
KCY1
≥ 2/f
CLK
300 1150
1150 ns
SCKp high-level width
t
KH1
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 20 pF, R
b
= 2.7 k
Ω
t
KCY1
/2
−
120
t
KCY1
/2
−
120
t
KCY1
/2
−
120
ns
SCKp low-level width
t
KL1
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 20 pF, R
b
= 2.7 k
Ω
t
KCY1
/2
−
10
t
KCY1
/2
−
50
t
KCY1
/2
−
50
ns
SIp setup time
(to SCKp
↑)
Note 4
t
SIK1
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 20 pF, R
b
= 2.7 k
Ω
121 479 479 ns
SIp hold time
(from SCKp
↑)
Note 4
t
KSI1
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 20 pF, R
b
= 2.7 k
Ω
10 10 10
ns
Delay time from SCKp
↓ to
SOp output
Note 4
t
KSO1
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 20 pF, R
b
= 2.7 k
Ω
130
130 130
ns
SIp setup time
(to SCKp
↓)
Note 5
t
SIK1
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 20 pF, R
b
= 2.7 k
Ω
33 110 110
ns
SIp hold time
(from SCKp
↓)
Note 5
t
KSI1
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 20 pF, R
b
= 2.7 k
Ω
10 10 10
ns
Delay time from SCKp
↑ to
SOp output
Note 5
t
KSO1
2.7 V
≤ EV
DD0
≤ 3.6 V, 2.3 V ≤ V
b
≤ 2.7 V,
C
b
= 20 pF, R
b
= 2.7 k
Ω
10 10 10
ns
Notes 1. HS is condition of HS (high-speed main) mode.
2. LS is condition of LS (low-speed main) mode.
3. LV is condition of LV (low-voltage main) mode.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
5. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (V
DD
tolerance (When 25- to
48-pin products)/EV
DD
tolerance (When 64-pin products)) mode for the SOp pin and SCKp pin by using
port input mode register g (PIMg) and port output mode register g (POMg). For V
IH
and V
IL
, see the DC
characteristics with TTL input buffer selected.
Remarks 1. R
b
[
Ω]: Communication line (SCKp, SOp) pull-up resistance, C
b
[F]: Communication line (SCKp, SOp) load
capacitance, V
b
[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
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