Fujitsu FR81S User Manual
CHAPTER 25: 16-BIT OUTPUT COMPARE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 16-BIT OUTPUT COMPARE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
18
4.1.3. Compare Mode Control Register (OCMOD)
The bit configuration of the compare Mode control register is shown below.
The compare mode control register (OCMOD) controls the output level upon detection of a compare match
by specifying to invert, set, or reset the output level.
•
OCMOD01: Address 1253
H
(Access: Byte, Half-word, Word)
•
OCMOD23: Address 125B
H
(Access: Byte, Half-word, Word)
•
OCMOD45: Address 1263
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
MOD1
MOD0
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R0,W0
R/W
R/W
[bit7 to bit2] Reserved
Always write 0 to these bits.
[bit1] MOD1: Compare match mode setting bit
MOD1
Function
0
Inverts the previous output value.
1
Sets the output value to "1" or resets it to "0" according to the setting of the CMOD bit in
the compare control register (OCS01).
⋅
This bit specifies the operation to be performed when a compare match is detected in the output compare
output 1.
⋅
When this bit is set to "0", the output value is inverted upon a compare match.
⋅
When this bit is set to "1", the output value is set to "1" or reset to "0" upon a compare match. The switch
between setting and resetting is performed according to the CMOD bit (common to ch.0 and ch.1) in the
compare control register (OCS01).
⋅
For ch.3 and 5, the operation is the same as ch.1.
Note:
Be sure to stop the compare operation before writing a value to this bit.
MB91520 Series
MN705-00010-1v0-E
973