Fujitsu FR81S User Manual
CHAPTER 34: CLOCK SUPERVISOR
4. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK SUPERVISOR
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
4. Operation
This section explains the operation of the clock supervisor.
After the clock replaces the CR oscillator, it is reset at once when the main clock stops while CPU is
working with the main clock. When the period of 30μs to 40μs and the clock is not input, it is judged that it
stops. Because the bit that shows the thing that the main clock stops remains in the register, the thing that
the problem occurs with software can be judged.
After the clock replaces the CR oscillator, it is reset at once when sub clock stops while CPU is working
with sub clock. When the period of 310μs to 320μs and the clock is not input, it is judged that it stops.
Because the bit that shows the thing that a sub clock stops remains in the register, the thing that the problem
occurs with software can be judged.
When sub clock stops while CPU is working with the main clock, reset is not generated at once. It operates
with the CR clock when changing to the sub clock mode. As for the stop of the sub clock, you can recognize
by reading the register.
The main clock supervisor stops automatically when the main clock is stopped intending it. When sub clock
is stopped intending it, the sub clock supervisor stops automatically.
The CR oscillator stops automatically when the standby mode changes when the CR oscillation at the
standby mode is prohibited. The CR oscillator reactivates automatically when returning from the standby
mode.
Note:
Please do not permit the PLL oscillation operation when the main clock is replaced with the CR oscillator
and works after detecting the main clock stop.
The following explains the operational mode of the clock supervisor.
MB91520 Series
MN705-00010-1v0-E
1182