Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
[bit31 to bit28] Reserved
Always write "0" to these bits.
[bit27 to bit24] RWT[3:0] (Read access auto WaiT) : Read Access Auto Wait
RWT[3:0] sets the number of auto wait cycles when fetching data during the read access cycle.
RWT[3:0]
Read access wait
0000
0 cycle
0001
1 cycle
0010
2 cycles
0011
3 cycles
:
:
1110
14 cycles
1111
15 cycles (AWR0 Initial value)
[bit23 to bit20] WWT[3:0] (Write access auto WaiT) : Write Access Auto Wait
WWT[3:0] sets the number of auto wait cycles during the write access cycle.
WWT[3:0]
Write access wait
0000
0 cycle (AWR0 Initial value)
0001
1 cycle
0010
2 cycles
0011
3 cycles
:
:
1110
14 cycles
1111
15 cycles
[bit19, bit18] RIDL[1:0] (Read access IDLe cycle) : Read Access Idle Cycle
RIDL[1:0] is configured in order to prevent conflicts on the data bus between the read data from a device
with a long output off time and the data of the subsequent access. If an access meeting any of the following
conditions occurs in sequence after a read access, the idle cycles specified in RIDL are inserted after the
read access.
· Write access
· Access to another CS area
· Access to a CS area configured with address/data multiplexed bus type
For the case of sequential read accesses to the same CS area configured with split bus type (ACR:BSTY=0),
idle cycles are not inserted by RIDL. During idle cycles, all CS signals are negated and the data pins are put
in the high-impedance state.
RIDL[1:0]
Read Access Idle Cycle
00
0 cycle (AWR0 Initial value)
01
1 cycle
10
2 cycles
11
3 cycles
MB91520 Series
MN705-00010-1v0-E
1212