Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
43
The flow for configuring CS is shown below.
Figure 5-9 CS Setting Flow
Disabling CS0
In order to change CS0, CS0 first needs to be disabled. Write 0x0 to ASR0 as a word.
Setting ACR
The bus width, bus type, etc. of the CS area can be configured.
1. The data bus width of the configured CS area can be selected from 8 bits and 16 bits.
2. The address output type can be selected from normal output and shift output.
3. The bus type can be selected from address/data split bus and address/data multiplexed bus.
The above setting values are written to ACR as word units.
Setting AWR
The parameters that determine the output timing of the external bus signals and whether the RDY pin
function is enabled or disabled can be configured. The setting values are written to AWR as words.
Yes
Yes
No
No
Set CS
Change the setting of CS0
or configure another CS area
in 0x00000000 to 0x7FFFFFFF
Disable CS0
(Write 0 to ASR0:CSEN)
Set ACR[i]
Set AWR[i]
Set ASR[i]
Enable CS[i]
Enable CS[i]
Read the value of ASR[i]
Finish setting CS[i]
(not setting other CS[i])
Compare the setting value
of ASR[i] to the read value
of ASR[i] to the read value
Finished setting CS
MB91520 Series
MN705-00010-1v0-E
1242