Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
44
Figure 5-10 Parameters that can be configured in AWR
A
S
C
Y
0
1
0
3
0
3
0
3
0
15
0
15
0
3
0
3
3
0
3
SYS
C
L
K
AS
X
RD
X
For address/
data split bus
For address/data
multiplexed bus
: H: Dxx is input. L: Dxx is output.
*
1
:
The valid value output of A00 to A21 and Dxx is extended by the number of cycles specified by RDCS during
read access and by WRCS during write access.
*2 : The valid value output of Dxx is extended by the number of cycles specified by WRCS during write access.
C
S
n
X
(
n
=
0
,
1
,
2
,
3
)
D
x
x
D
x
x
W
R
n
X
(n=
0
,1
)
A00 to A21
A
C
S
[
1
:
0
]
R
I
D
L
[
1
:
0
]
o
r
W
R
C
V
[
1
:
0
]
CSRD[1:0]
RWT[3:0]
RDCS[1:0]
0
CSWR[1:0]
WWT[3:0]
*1
WRCS[1:0]
*2
data
A
D
C
Y
[
1
:
0
]
address
MB91520 Series
MN705-00010-1v0-E
1243