Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4.12.
PLL/SSCG Output Clock Division Setting Register : CCPSDIVR (CCtl Pll/Sscg clock
DIVision Register) ......................................................................................................... 191
4.13.
PLL Feedback Division Setting Register : CCPLLFBR (CCtl PLL FB clock division
Register) ....................................................................................................................... 193
4.14.
SSCG Feedback Division Setting Register 0 : CCSSFBR0 (CCtl SScg FB clock division
Register 0) .................................................................................................................... 194
4.15.
SSCG Feedback Division Setting Register 1 : CCSSFBR1 (CCtl SScg FB clock division
Register 1) .................................................................................................................... 195
4.16.
SSCG Configuration Setting Register 0 : CCSSCCR0 (CCtl SSCg Config. Register 0)196
4.17.
SSCG Configuration Setting Register 1 : CCSSCCR1 (CCtl SSCg Config. Register 1)198
4.18.
Clock Gear Configuration Setting Register 0 : CCCGRCR0 (CCtl Clock Gear Config.
Register 0) .................................................................................................................... 199
4.19.
Clock Gear Configuration Setting Register 1 : CCCGRCR1 (CCtl Clock Gear Config.
Register 1) .................................................................................................................... 201
4.20.
Clock Gear Configuration Setting Register 2 : CCCGRCR2 (CCtl Clock Gear Config.
Register 2) .................................................................................................................... 202
4.21.
RTC/PMU Clock Selection Register : CCRTSELR (CCtl RTc pmu clock Selection
Register) ....................................................................................................................... 203
4.22.
PMU Clock Division Setting Register 0 : CCPMUCR0 (CCtl PMU Clock division Register
0) .................................................................................................................................. 205
4.23.
PMU Clock Division Setting Register 1 : CCPMUCR1 (CCtl PMU Clock division Register
1) .................................................................................................................................. 206
4.24.
Sync/Async Control Register : SACR ............................................................................ 208
4.25.
Peripheral Interface Clock Divider : PICD ..................................................................... 209
5.
O
PERATION
.................................................................................................................................. 211
5.1.
Oscillation Control .......................................................................................................... 212
5.1.1.
Main Clock (MCLK) ................................................................................................................................. 213
5.1.2.
Sub Clock (SBCLK) ................................................................................................................................. 214
5.1.3.
PLL/SSCG Clock (PLLSSCLK) ............................................................................................................. 215
5.1.4.
Limitations when PLL/SSCG Clock is used ......................................................................................... 218
5.2.
Oscillation Stabilization Wait .......................................................................................... 219
5.2.1.
Conditions for Generating Stabilization Wait Time .............................................................................. 220
5.2.2.
Selecting Stabilization Wait Time ........................................................................................................... 221
5.2.3.
End of the Stabilization Wait Time ......................................................................................................... 222
5.3.
Selecting the Source Clock (SRCCLK) ......................................................................... 223
5.3.1.
Selecting the Source Clock at the Time of Initialization ..................................................................... 224
5.3.2.
Procedure of switching the source clock .............................................................................................. 225
5.4.
Timer .............................................................................................................................. 230
5.4.1.
Main Clock Oscillation Stabilization Wait Timer (Main Timer) ........................................................... 231
5.4.2.
Sub Clock Oscillation Stabilization Wait Timer (Sub Timer) .............................................................. 232
5.4.3.
PLL/SSCG Clock Oscillation Stabilization Wait timer (PLL Timer) ................................................... 233
5.4.4.
Setting ....................................................................................................................................................... 234
5.4.5.
Procedure for Setting the Timer Interrupt ............................................................................................. 235
5.4.6.
Timer Operations ..................................................................................................................................... 236
5.4.7.
Watch Mode and Timer Interrupt ........................................................................................................... 237
5.5.
Notes when Clocks Conflict ........................................................................................... 238
5.6.
The Clock Gear Circuit .................................................................................................. 239
5.6.1.
Procedure of Gear Up ............................................................................................................................. 240
5.6.2.
Procedure of Gear Down ........................................................................................................................ 241
5.7.
Operations during MDI Communications ....................................................................... 242
5.8.
About PMU clock (PMUCLK) ......................................................................................... 243
CHAPTER 6: CLOCK RESET STATE TRANSITIONS ...................................................................... 245
1.
O
VERVIEW
.................................................................................................................................. 246
2.
D
EVICE
S
TATES AND
T
RANSITIONS
................................................................................................ 247
2.1.
Diagram of State Transitions .......................................................................................... 248
2.2.
Explanation of Each States ............................................................................................ 250
2.3.
Priority of State Transition Requests .............................................................................. 252
3.
D
EVICE
S
TATE AND
R
EGULATOR
M
ODE
C
ORRESPONDING TO THOSE
S
TATES
.................................. 253
MB91520 Series
MN705-00010-1v0-E
(11)