Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
51
Bit name
Function
bit2 RDRF:
Reception data full flag bit
"0" Read: Receive data register (RDR) is empty
"1" Read: The received data register (RDR) contains data.
⋅
The flag indicates the state of the receive data register (RDR).
⋅
When received data is loaded in RDR, this flag will be set to "1" and
when RDR is read out, it will be cleared to "0".
⋅
When the RDRF bit and SCR:RIE bit are set to "1", a reception interrupt
request will be output.
⋅
While using reception FIFO, the RDRF will be set to "1" once the
reception FIFO has received the specified number of data sets.
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In the case where all the conditions below are met while using reception
FIFO, when reception idle continues for more than 8 baud rate clocks,
RDRF will be set to "1".
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Reception FIFO idle detection enable bit (FCR1:FRIIE) is set to “1”
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The reception FIFO contains data without receiving the specified number
of data sets
If you read the RDR while the counter is counting 8 baud rate clocks, the
counter will be reset to 0 and start counting 8 clocks again.
⋅
While using reception FIFO, the bit will be cleared to "0" once the
reception FIFO becomes empty.
bit1 TDRE:
Transmission data empty
flag bit
"0" Read: Transmit data register (TDR) contains data.
"1" Read: Transmit data register is empty
⋅
The flag indicates the state of the transmit data register (TDR).
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When a transmit data is written to TDR, this flag turns to "0", which
indicates that a valid data exists in the TDR. Once a transmission starts
after data being loaded to the transmit shift register, the bit will be set to
"1", which indicates that the TDR does not contain any valid data.
⋅
When the TDRE bit and the SCR:TIE bit are set to "1", a transmission
interrupt request will be output.
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When you set the UPCL bit of the serial control register (SCR) to "1",
the TDRE bit will be set to "1".
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For details of the timing of setting/resetting the TDRE bit while using
transmission FIFO, see Section "36.5.1.5 Interrupts When Using
Transmission FIFO and Flag Setting Timing".
bit0 TBI:
Transmission bus idle flag
bit
"0" Read: Transmission is in progress.
"1" Read: No transmission operation
⋅
This bit indicates CSIO has no transmission in progress.
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When transmission data has been written to the transmit data register
(TDR), this bit will become "0".
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When the transmit data register (TDR) is empty (TDRE=1) and no
transmission is in progress, this bit will be set to "1".
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When you set the UPCL bit of the serial control register (SCR) to "1",
the TDRE bit will be set to "1".
⋅
When this bit is "1" and transmission bus idle interrupts are enabled
(SCR:TBIE=1), a transmission interrupt request will be output.
Note:
This bit becomes “1” when transmission data register (TDR) is empty
(TDRE=1) and serial chip select error (CSE=1) is generated.
MB91520 Series
MN705-00010-1v0-E
1364