Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
189
Notes:
⋅
When chip select is used, chip select error flag (SACSR:CSE) will be set to "1" after hold delay time is
passed after a chip select error is generated and at the same time, the serial chip select pin will become
inactive. No transmission will be started even if transmitting data is written to the transmission data
register (TDR) during hold delay time, and the chip select error flag (SACSR:CSE) will be set to "1"
after hold delay time is passed.
⋅
While the chip select error flag (SACSR:CSE) is set to "1", no transmission will be started even if
transmitting data is written to the transmission data register (TDR).
⋅
When the chip select error flag (SACSR:CSE) is set to "1" while synchronous transmission is used with
the serial timer, no transmission will be started even if serial timer register (STMR) matched the serial
timer comparison register.
⋅
When the chip select error flag (SACSR:CSE) is set to "1" while synchronous transmission is used with
the serial timer, no transmission will be started even if serial timer register (STMR) matched the serial
timer comparison register.
Slave Mode (SCR:MS="1")
Chip select error will be generated when chip select pin becomes inactive while transmitting
(SSR:TBI="0").
In this case, when chip select error interrupt is enabled (SACSR:CSEIE="1"), a transmission interrupt will
be generated.
Figure 6-7 Chip Select Error Generation Timing
D1
D0
SCK
SOUT
TDRE
TDR_RW
TXE
SCS input
D2 D3 D4 D5 D6
TBI
CSE
Generation of transmission
interrupt
MB91520 Series
MN705-00010-1v0-E
1502