Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

6. Operation of CSIO

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

230

Notes:

⋅

If the transmission is disabled (SCR:TXE="0") and the software reset is set (SCR:UPCL=1) when the

serial chip select pin is active, the serial chip select pin become inactive.

⋅

If the transmission data is written to the hold delay time of the serial chip select pin, the pin does not

become inactive and the next transmission data is sent.

⋅

When the serial chip select pin does not maintain its active state (SCSCR:SCAM=0) and becomes

inactive, transmission bus idle (SSR:TBI=1) is set.

⋅

If SCSCR:CSEN3 to CSEN0 is set to "0000b" in master mode (SCR:MS=0), transmission/reception

operation is performed regardless of the serial chip select pin.

⋅

If the transmit data register (TDR) has no valid transmission data (SSR:TDRE=1) when 1 frame

transmission is completed during sending frames less than TBYTE setting, the following operation will

be performed.

⋅

When the transfer byte error is enabled (TBEEN=1), a chip select error (SACSR:CSE=1) occurs.

After the hold delay time has passed since the chip select error (SACSR:CSE=1) occurred, the serial

chip select pin become inactive. When the chip select error flag (SACSR:CSE) is set to "1", writing

the transmission data to the transmission data register (TDR) does not start transmission operation.

⋅

When the transfer byte error is disabled (TBEEN=0), transmission operation will be stopped until

transmission data is written to the transmission data register (TDR). At this time, the serial chip select

pin is active. Transmission operation will be restarted when transmission data is written to the

transmission data register (TDR).



Operation of slave mode (SCR:MS="1")

When the serial chip select pin 0 (SCS0) is enabled (SCSCR:CSEN0="1") and the serial chip select pin

input become active, the transmission or reception operation is performed in synchronization to the serial

clock (SCK). Then, when the serial chip select pin input becomes inactive, the transmission or reception

operation is terminated.

Figure 6-23 Operation of Serial Chip Select in Slave Mode (Slave Transmission, SCINV="0")

Notes:

⋅

It does not operate even if the serial clock is input when the serial chip select pin input is inactive.

⋅

If the serial chip select input becomes inactive before sampling a bit at the end during reception operation,

the data being received is deleted.

⋅

If the serial chip select input becomes inactive during transmission operation, the data being transmitted

is deleted and the chip select error occurs (SACSR:CSE).

⋅

When the serial chip select pin input becomes inactive, the transmission bus idle (SSR:TBI=1) is set.

⋅

If SCSCR:CSEN0 is set to "0" in slave mode (SCR:MS=1), transmission/reception operation is

performed regardless of the serial chip select pin.

SCK

SCS input

D３ D４

Transmission data

(ＳＰＩ＝０)

Transmission data

(ＳＰＩ＝１)

TDR RW

TBI

MB91520 Series

MN705-00010-1v0-E

1543