Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
249
Figure 7-3 Timing of Interrupt Generation
Timing to generate reception interrupt when reception FIFO is used
Reception data
FIFOBYTE(reception)
RDRF
7
th
Byte
9
Generation of interrupt by the match of number of FBYTE (reception)
setting and number of reception data
setting and number of reception data
Reading RDR
8
th
Byte
Check Sum
ST
SP
ST
SP
ST
SP
Reading of all reception data
Valid byte display
6 7 8 0
DATA Field
Check Sum Field
Synch Break
Timing to set ORE (overrun error) flag bit
Reception data
FIFOBYTE(reception)
RDRF
62
nd
Byte
62
(note)
An overrun error will occur if the next data is received when FBYTE display indicates FIFO capacity.
The figure shows that 64-byte of FIFO capacity is used.
The figure shows that 64-byte of FIFO capacity is used.
63
rd
Byte
64
th
Byte
65
th
Byte
ST
SP
ST
SP ST
SP
ST
SP
ST 66
th
Byte SP
61 62 63 64
Valid byte display
ORE
Overrun error occurrence
MB91520 Series
MN705-00010-1v0-E
1562