Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
7. Operation of LIN Interface (v2.1)
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
296
Figure 7-43 From ID Field transmission to DATA Field transmission (FIFO unused when ID
register is not used)
register is not used)
Sync Field
ID Field
data Field
LAMCR : LAMEN
LAMCR : LIDEN
H : LIN assist mode processing enable
L : TDR use
LAMTID : LID5-0
：Don’t care
checksum
Data 1
Data N
LIN bus
6 7 SP ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3
0 1 2 3 4 5 6
SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7
SP
7
ST
Data (N-1）
LAMSR : LCSC
SSR : TDRE
DATA Field write
TDR
Data 1
Data 2
Data N
ID Field value
LAMSR : LAHC
(When DATA Field is received)
When LIN assist mode transmission register (LAMTID) is not used, please do not write data though
SSR:TDRE is set to "1" when the first bit of ID Field is transmitted.
Moreover, please make it to transmission interrupt prohibition (SCR:TIE="0").
Moreover, please make it to transmission interrupt prohibition (SCR:TIE="0").
When LIN assist mode transmission register (LAMTID) is used, please do not write data though it is
possible to write in DATA Field after LIN Break Field setting bit (SCR:LBR) is set to "1".
Please set the reception enable (SCR:RXE=1) from LIN Break Field detection (SSR:LBD=1) to the
response reception starting.
When DATA Field is reception, SSR:RDRF is set to 1. At this time, if reception interrupt enable
(SSR:RIE="1") is done, the reception interrupt is generated.
When the reception of checksum is completed, the LIN checksum arithmetic operations completion flag
is set (LAMSR:LCSC="1"). At this time, when the checksum arithmetic operations completion interrupt
enable bit has been enabled (LAMIER:LCSCIE="1"), the interrupt is generated.
enable bit has been enabled (LAMIER:LCSCIE="1"), the interrupt is generated.
After the checksum reception is completed (LAMSR:LCSC=1), reception prohibition setting
(SCR:RXE=0) is done.
Detection of the start bit is as follows; the falling edge is detected after passing through the noise filter
(which samples serial data input in 3 bus clock and decides the value by majority), and the data "L" is
detected after the noise filter at the sampling point.
detected after the noise filter at the sampling point.
Figure 7-44 From ID Field transmission to DATA Field reception (FIFO unused when ID
register is used)
register is used)
SSR : RDRF
Sync Field
DATA Field read
ID Field
data Field
LAMCR : LAMEN
LAMCR : LIDEN
H : LIN assist mode processing enable
H : LIN ID register use enable
LAMTID : LID5-0
LIN ID value setting
RDR
Data 1
Data (N-2)
checksum
Data 1
Data N
LIN bus
6 7 SP ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3
0 1 2 3 4 5 6
SP ST 0 1 2 3 4 5 6 7 SP
ST 0 1 2 3 4 5 6 7
SP
7
ST
Data (N-1）
SSR : TDRE
Data (N-1)
Data N
LAMSR : LCSC
：Don’t care
LAMSR : LAHC
MB91520 Series
MN705-00010-1v0-E
1609