Fujitsu FR81S User Manual

CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE

7. Operation of LIN Interface (v2.1)

FUJITSU SEMICONDUCTOR LIMITED

CHAPTER : MULTI-FUNCTION SERIAL INTERFACE

FUJITSU SEMICONDUCTOR CONFIDENTIAL

302



Slave operation



Automatic header reception setting

Please set it to reception an automatic header in the assist mode as follows.

⋅

Please set the SCR:MS bit to "1" to operate as a slave.

⋅

Please set the LAMCR:LAMEN bit to "1" to operate as LIN assist mode.

⋅

The ID Field value is written in LAMRID (LIN assist mode reception ID register) or RDR (reception

data register). Please set the LAMCR:LIDEN bit to "1" when you write the value of ID Field in

LAMRID. Please set the LAMCR:LIDEN bit to "0" when writing it in RDR.

⋅

Please set the SACSR:AUTE bit to "1" when you do the baud rate adjustment automatically.

⋅

Please set reception enable bit (SCR:RXE) to "1" (reception enable).



From LIN Break Field reception to ID Field reception

1. When LIN Break Field is input, LIN Break Field is detected in the 11th bit (SSR:LBD=1). At this time,

if the ESCR:LBIE bit is set to "1", the interrupt is generated. Please set the ESCR:LBIE bit to "0", and

prohibit the status interrupt in the LIN assist mode.

Operation when the automatic baud rate is adjusted is shown below.

2. When LIN interface (v2.1) detected the first falling edge of Sync Field, the serial timer register

(STMR) is initialized to 0.

3. When the fifth falling edge of Sync Field is detected, sync field detection flag (SACSR:SFD) is set to

"1". At this time, if the SACSR:SFDE bit is set to "1", the status interrupt is generated. Please set the

ESCR:SFDE bit to "0", and prohibit the status interrupt in the LIN assist mode.

4. When the fifth falling edge of Sync Field is detected, it operates according to the value of the serial

timer register (STMR) as follows.

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When the value of the serial timer register (STMR) is the sync field lower limit register (SFLR) or

larger and the sync field upper limit register (SFUR) or smaller, the value of the serial timer register

(SMTR) will be set to the baud rate generator register (BGR) and the baud rate setting flag

(SACSR:BST) will be set to "1".

⋅

When the value of the serial timer register (STMR) is smaller than the sync field lower limit register

(SFLR) or larger than the sync field upper limit register (SFUR), the value of the baud rate generator

Figure 7-54 From LIN Break Field reception to ID Field reception (STMR is SFUR or smaller,

and SFLR or larger).

LIN Break

delimiter

Sync Field

ST 0 1 2 3 4 5 6 7 SP ST 0 1 2 3 4 5 6 7 SP

ID Field

LIN bus

(1)

(2)

(3)(4)

SACSR : BST

BGR1, BGR0

LAMSR : LAHC

ST 0 1 2 3 4 5 6 7 SP

data

Figure 7-55 From LIN Break Field reception to ID Field reception (STMR is smaller than

SFUR, and larger than SFLR).