Fujitsu FR81S User Manual
CHAPTER 3: CPU
10. Memory Protection Function (MPU)
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CHAPTER : CPU
FUJITSU SEMICONDUCTOR CONFIDENTIAL
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10.3.4.
Data Access Protection Violation Address
Register :DPVAR
Register :DPVAR
The bit configuration of the data access Protection violation address register is shown.
The address where the violation of the data access protection occurs is saved.
DPVAR : Address 0320
H
(Access : Word)
bit31
bit30
• • •
bit2
bit1
bit0
DPVA[31:0]
Initial value
X
X
• • •
X
X
X
Attribute R,WX R,WX
• • •
R,WX R,WX R,WX
[bit31 to bit0] DPVA[31:0] (Data Access Protection Violation Address)
This register stores the address where a data access protection violation occurred when a violation has not
occurred in the data access protection violation status register (DPVSR.DPV =0). This register indicates the
address requested by the CPU, and the address is not aligned.
MB91520 Series
MN705-00010-1v0-E
131