Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
359
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When the master device is receiving data and the DMA mode is enabled (SSR:DMA=1) and when
dummy data is written in the TDR register, the next data will be received with the transmission bus
idle flag (SSR:TBI) still "0" when SSR:TDRE bit is "0" at the timing when the transmission bus idle
flag (SSR:TBI) becomes "1".
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If data is received when the reception FIFO is enabled and IBCR:WSEL="0", the SSR:RDRF bit
becomes "1" after the last bit is received and the interrupt flag (IBCR:INT) becomes "1" after ACK is
transmitted.
Figure 8-33 Master Reception Interrupt (1)-when FIFO is Disabled
(SSR:DMA="0", IBCR:WSEL="0", IBSR:RSA="0")
S Slave Address R ACK Data ACK Data ACK Data NACK P or Sr
△ △ △ △▲
① ② ③ ④
S: Start condition
R: Data direction bit (Read direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of INTE = "1"
: Interrupt because of CNDE = "1"
(1) An interrupt generated by slave address transmission + direction bit transmission +
acknowledgment reception
- Interrupt is cleared to "0" by writing INT = "0"
(2) An interrupt generated by 1 byte reception + acknowledgment transmission
- Write INT ="0" after the reception data is read
(3) An interrupt generated by 1 byte reception + acknowledgment transmission
- Set ACKE = "0" and then write INT = "0" after the reception data is read
(4) An interrupt generated by 1 byte reception + acknowledgment transmission
- Set MSS = "0" or MSS = "1" and SCC = "1"
*: The TDRE bit is "1" upon the generation of the interrupt flag (INT)
Figure 8-34 Master Reception Interrupt (2)-when FIFO is Disabled
(SSR:DMA="0", IBCR:WSEL="1", IBSR:RSA="0")
S Slave Address R ACK Data ACK Data ACK Data NACK P or Sr
△ △ △ △ ▲
① ② ② ③
S: Start condition
R: Data direction bit (Read direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of INTE = "1"
: Interrupt because of CNDE = "1"
(1) Generation of interrupt by slave address transmission, direction bit transmission and
acknowledgement reception:
- Clears interrupt to "0" after writing "0" to INT
(2) Generation of interrupt by 1-byte reception:
- Writes "0" to INT after reading reception data
(3) Generation of interrupt by 1-byte reception:
- Sets "0" to ACKE and sets MSS="0", MSS="1" or SCC="1" after reading reception data
*: The TDRE bit is "1" upon the generation of the interrupt flag (INT)
MB91520 Series
MN705-00010-1v0-E
1672