Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
8. Operation of I2C
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
372
Figure 8-52 Slave Reception Interrupt (11)-when FIFO is Enabled
(SSR:DMA="1", IBSR:RSA="0")
S Slave Address W ACK Data ACK Data ACK Data ACK P or Sr
▲
① ②
S: Start condition
W: Data direction bit (Write direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of CNDE = "1"
(1) The I
2
C bus wait according to becoming of reception FIFO Full.
- Releases waiting if it reads out data from reception FIFO even once.
(2) An interrupt generated by the detection of a stop condition or a repeated start condition
- Read all data from reception FIFO
Figure 8-53 Slave Reception Interrupt (12)-when FIFO is Enabled
(SSR:DMA="1", IBCR:WSEL="0", IBSR:RSA="1")
S Slave Address W ACK Data ACK Data ACK Data ACK P or Sr
△ ■ ■ ■▲
① ② ② ③
S: Start condition
W: Data direction bit (Write direction)
P: Stop condition
Sr: Repeated start condition
: Interrupt because of INTE = "1"
: Interrupt because of CNDE = "1"
n: Interrupt by RIE = "1"
(1) Interrupt generated by reserved address ("0000xxxx" or "1111xxxx") is match
- Receive data is read. ACKE="1", INT="0" write
(2) An interrupt generated by 1 byte reception + acknowledge output
- Receive data is read.
(3) An interrupt generated by 1 byte reception + acknowledge output
- Receive data is read.
MB91520 Series
MN705-00010-1v0-E
1685