Fujitsu FR81S User Manual
CHAPTER 41: CAN
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
80
5.5. Interrupt Function
Interrupt function is shown.
This section explains the processing of status interrupt (IntId=8000
H
) and message interrupt (IntId=message
number).
If 2 or more interrupts are pending, the CAN interrupt register (INTR) will indicate the pending interrupt
code of the highest priority interrupt. High priority interrupt codes will always be displayed, ignoring the
chronological order in which the interrupt codes were set. Interrupt code will be held until it is cleared by
CPU.
Status interrupt (IntId bit = 8000
H
) has the highest priority.
Priority of message interrupts becomes higher as the message number gets smaller, and vice versa.
Message interrupt will be cleared when the IntPnd bit of the message object is cleared. Status interrupt will
be cleared when the CAN status register (STATR) is read.
the IntPnd bit of the CAN interrupt pending register (INTPND) indicates whether any interrupt exists. The
IntPnd bit will indicate "0" if there is no pending interrupt.
The interrupt signal to the CPU will become active when the IndPnd bit becomes "1" while the IE bit of the
CAN control register (CTRLR) and TxIE and RxIE bits of the IFx message control register (IFxMCTR) are
set to "1". The interrupt signal maintains its active state until the CAN interrupt pending register (INTPND)
is cleared to "0" (interrupt factor reset) or until IE bit of the CAN control register (CTRLR) is reset to "0".
the CAN interrupt register (INTR) being set to "8000
H
" indicates an update of the CAN status register
(STATR) by the CAN controller; and this interrupt will have the highest priority. The interrupt generated by
updating the CAN status register (STATR) can allow or prohibit the setting of the CAN interrupt register
(INTR) by using EIE and SIE bits of the CAN control register (CTRLR). Interrupt signal to the CPU can be
controlled by the IE bit of the CAN control register (CTRLR).
The RxOk bit, TxOk bit and LEC bit of the CAN status register (STATR) can be updated (reset) by a write
from the CPU. However, interrupt cannot be set or reset by the write operation.
The CAN interrupt register (INTR) set to other than "8000
H
" and "0000
H
" indicates that the message
interrupt is currently pending and that it has a high priority.
The CAN interrupt register (INTR) will be updated even when IE has been reset.
Message interrupt factor to the CPU can be confirmed in the CAN interrupt register (INTR) or CAN
interrupt pending register (INTPND).(See "4.5 Message Handler Registers".) When clearing a message
interrupt, it is possible to read the message data at the same time. When the message interrupt specified by
the CAN interrupt register (INTR) is cleared, the next priority interrupt will be set to the CAN interrupt
register (INTR), waiting for the next interrupt process. The CAN interrupt register (INTR) will indicate
"0000
H
" if there is no interrupt.
Notes:
⋅
Status interrupt (IntId=8000
H
) will be cleared by a read access from the CAN status register (STATR).
⋅
Status interrupt (IntId=8000
H
) by a write access to the CAN status register (STATR) will not be
generated.
MB91520 Series
MN705-00010-1v0-E
1773