Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
4.3. Division Configuration Register 2 : DIVR2 (Division
clock configuration Register 2)
The bit configuration of the division configuration register 2 is shown.
This register controls division of clocks.
DIVR2 : Address 048A
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DIVP[3:0]
Reserved
Initial value
0
0
1
1
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7 to bit4] DIVP[3:0] (Division ratio of PCLK) : Peripheral clock division setting
These bits configure the division ratio when generating the peripheral clock (PCLK) from the base clock.
DIVP[3:0]
Base clock → PCLK division ratio
0000
No divide
0001
2 division
0010
3 division
0011
4 division (Initial value)
0100
5 division
0101
6 division
0110
7 division
0111
8 division
1000
9 division
1001
10 division
1010
11 division
1011
12 division
1100
13 division
1101
14 division
1110
15 division
1111
16 division
Note:
Set this register to peripheral clock (PCLK) to be sure to become 40MHz or less.
[bit3 to bit0] (Reserved)
MB91520 Series
MN705-00010-1v0-E
174