Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
14
4.4. Clock Source Selection Register : CSELR (Clock
source Selection Register)
The bit configuration of the division selection register 0 is shown.
This register selects a control and a source clock (SRCCLK) for each clock source.
CSELR : Address 0510
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SCEN
PCEN
MCEN
Reserved
CKS[1:0]
Initial value
*
0
1
0
0
0
0
0
Attribute
R,W
R,W
R,W
R0,WX
R0,WX
R0,WX
R,W
R,W
*: This bit is initialized to “0”. But this bit is not initialized by the return from the watch mode
(power-shutdown).
Note:
The value set for this register and the value read out from this register are not actually controlled and selected.
You can make sure that the value set for this register would really take effect by reading out CMONR. After
making sure that the value of this register is the same as that of CMONR, rewrite the register. While switching
clocks is in progress (CKS[1:0] ≠ CKM[1:0]), a write operation to this register will be ignored.
[bit7] SCEN (Sub Clock ENable) : Sub clock oscillation enable
This bit controls an oscillation circuit for sub clock (SBCLK) as follows.
SCEN
Oscillation control for sub clock
0
Stop oscillation
(Initial value)
1
Oscillate
This bit cannot be rewritten when a sub clock (SBCLK) is selected as the source clock.
The oscillation circuit for sub clock always stops in stop mode regardless of the value of this bit.
The sub timer is cleared when this bit is set to "0".
[bit6] PCEN (PLL Clock ENable) : PLL oscillation enable
This bit controls the PLL/SSCG clock oscillation circuit as follows .
PCEN
Oscillation control for PLL/SSCG clock (PLLSSCLK)
0
Stop oscillation
(Initial value)
1
Oscillate
This bit cannot be rewritten when a PLL/SSCG clock (PLLSSCLK) is selected as the source clock. Also, this
bit cannot be rewritten when the main oscillation is stopped or during the main oscillation stabilization wait
time (CMONR. MCRDY=0).
Set this bit to "0" before switching to the stop mode.
Rewriting the MCEN bit with "0" causes this bit to set to "0".
MB91520 Series
MN705-00010-1v0-E
175