Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
4.2. Division Configuration Register 1 : DIVR1 (Division
clock configuration Register 1)
The bit configuration of the division configuration register 1 is shown.
This register controls division of clocks.
DIVR1 : Address 0489
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TSTP
DIVT[2:0]
Reserved
Initial value
0
0
0
1
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7] TSTP (TCLK SToP) : External bus clock stop enable
This bit configures whether to stop the external bus clock (TCLK) when going into sleep mode.
TSTP
TCLK in sleep mode
0
No stop (Initial value)
1
Stop
[bit6 to bit4] DIVT[2:0] (DIVide ratio of TCLK) : External bus clock division setting
These bits configure the division ratio when generating the external bus clock (TCLK) from the base clock.
DIVT[2:0]
Base clock → TCLK division ratio
000
No divide
001
2 division (Initial value)
010
3 division
011
4 division
100
5 division
101
6 division
110
7 division
111
8 division
Note:
Set this register so that the external bus clock (TCLK) definitely becomes 40MHz or less.
[bit3 to bit0] (Reserved)
MB91520 Series
MN705-00010-1v0-E
173