Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
[bit6] MTIE (Main clock Timer Interrupt Enable) : Main timer interrupt enabled
This bit controls interrupts by main timer overflow as follows.
MTIE
Main timer interrupt
0
Interrupt disabled (Initial value)
1
Interrupt enabled (outputs the interrupt request at the time when the MTIF bit is
"1")
[bit5] MTC (Main clock Timer Clear) : Main timer clear
This bit clears the main timer.
MTC
Write
Read
0
Does nothing.
Operating normally
1
Clear the main timer.
Clearing the main timer
This bit automatically returns to "0" after writing "1".
For read-modify-write instructions, "0" will be read out.
When writing MTC=1 at the time of MTC=1, the second write will be ignored.
[bit4] MTE (Main clock Timer Enable) : Main timer operation enable
This bit controls the operation of the main timer as follows.
MTE
Main timer operation
0
Operation disabled (Initial value)
1
Operation enabled
At the time of MTC=1, MTE=1 write is prohibited.
When you perform a PLL/SSCG clock oscillation stabilization wait, make sure to set this bit to "0" and stop
the main timer.
[bit3 to bit0] MTS[3:0] (Main clock Timer interval selection) : Main timer interval selection
These bits select the overflow interval of the main timer as follows.
MTS[3:0]
Main timer overflow interval
At 4MHz
1000
2
9
× main clock cycle
128.0[µs]
1001
2
10
× main clock cycle
256.0[µs]
1010
2
11
× main clock cycle
512.0[µs]
1011
2
12
× main clock cycle
1024.0[µs]
1100
2
13
× main clock cycle
2048.0[µs]
1101
2
14
× main clock cycle
4096.0[µs]
1110
2
15
× main clock cycle
8192.0[µs]
1111
2
16
× main clock cycle (Initial value)
16384.0[µs]
The MTS3 always reads "1".
Change MTS[3:0] at the time when the main timer stops (MTE=0).
MB91520 Series
MN705-00010-1v0-E
181