Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
22
[bit6] STIE (Sub clock Timer Interrupt Enable) : Sub timer interrupt enable
This bit controls interrupts by sub timer overflow as follows.
STIE
Sub timer interrupt
0
Interrupt disabled
(Initial value)
1
Interrupt enabled (output the interrupt request at the time STIF bit is "1")
[bit5] STC (Sub clock Timer Clear) : Sub timer clear
This bit clears the sub timer.
STC
Write
Read
0
Does nothing.
Operating normally
1
Clear the sub timer.
Clearing the sub timer
This bit automatically returns to "0" after writing "1".
For read-modify-write instructions, "0" will be read out.
When writing STC=1 at the time of STC=1, the second write will be ignored.
[bit4] STE (Sub clock Timer Enable) : Sub timer operation enabled
This bit controls the operation of the sub timer as follows.
STE
Sub timer operation
0
Operation disabled
(Initial value)
1
Operation enabled
At the time of STC=1, STE=1 write is prohibited.
[bit3] (Reserved)
[bit2 to bit0] STS[2:0] (Sub clock Timer interval selection) : Sub timer interval selection
These bits select the overflow interval of the sub timer as follows.
STS[2:0]
Sub timer overflow interval
At 32kHz
At CR clock
selected
000
2
8
×
sub clock cycle
8[ms]
5.12[ms]
001
2
9
×
sub clock cycle
16[ms]
10.24[ms]
010
2
10
×
sub clock cycle
32[ms]
20.48[ms]
011
2
11
×
sub clock cycle
64[ms]
40.96[ms]
100
2
12
×
sub clock cycle
128[ms]
81.92[ms]
101
2
13
×
sub clock cycle
0.256[s]
163.84[ms]
110
2
14
×
sub clock cycle
0.512[s]
327.68[ms]
111
2
15
×
sub clock cycle
(Initial value)
1.024[s]
655.36[ms]
MB91520 Series
MN705-00010-1v0-E
183