Fujitsu FR81S User Manual
CHAPTER 51: TIMING PROTECTION UNIT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : TIMING PROTECTION UNIT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
17
[bit29] CONT (Continue) : Timer operation restart
This bit is used to instruct timer to restart. The readout value is always 0.
When the operation is restarted by this bit, operation is restarted from the count value that has stopped.
When START, STOP, and the CONT bit are set at the same time, priority is judged in order of START >
CONT > STOP.
Writing 0 to the bit cause no influence in operation.
[bit28] IES (Interrupt Enable Set) : Interrupt enable bit Set
This bit is used to instruct to set timer interrupt enable. The interrupt enable bit (TPUTIE.IE[n]) is set by
writing 1 in this bit.
The readout value is always 0. Writing 0 to the bit cause no influence in operation.
[bit27] IEC (Interrupt Enable Clear) : Interrupt enable bit clear
This bit is used to instruct to clear timer interrupt enable. The interrupt enable bit (TPUTIE.IE[n]) is cleared
by writing 1 in this bit.
The readout value is always 0. Writing 0 to the bit cause no influence in operation.
[bit26] IRC (Interrupt Request Clear) : Interrupt request clear
This bit is used to instruct timer interrupt clear request . The interrupt request (TPUIR.IR[n]) is cleared by
writing 1 to this bit.
The readout value is always 0. Writing 0 to the bit cause no influence in operation.
[bit25 to bit24] (Reserved) : (Reserved bit)
These bits are reserved bit. When writing to those bits, 0 must be set. The readout value is 0.
[bit23 to bit0] ECPL[23:0] (End Count or Pre Load) : Counter End value or pre load value
The value used as the end value or pre-load value of the counter is set.
ECPL[23:0] is used as the end value of the counter in the normal mode.
ECPL[23:0] is used as pre-load value in the overflow mode.
MB91520 Series
MN705-00010-1v0-E
2184