Fujitsu FR81S User Manual
CHAPTER 51: TIMING PROTECTION UNIT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : TIMING PROTECTION UNIT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
18
4.10. TPU Timer Control Register 10 to 17 : TPUTCN10 to 17
The bit configuration of TPU timer control register 10 to 17 is shown below.
TPUTCN10 to TPUTCN17 : Address 0950
H
to 096C
H
(Access : Byte, Half-word,
Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PL
FRT
TMOD
PS[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute
R0,W0
R0,W0
R0,W0
R/W
R/W
R/W
R/W
R/W
It is a control register for each timer.
[bit7 to bit5] (Reserved) : (Reserved bit)
These bits are reserved bit. When writing to those bits, 0 must be set. The readout value is 0.
[bit4] PL (Pre-Load) : Pre-Load instructions
This bit is used to specify pre-load of ECPL[23:0] when the timer operation is started. This bit is effective
when the timer is in the overflow mode.
PL
Pre-load
0
Pre-load invalid
1
Pre-load valid
[bit3] FRT (Free-Running Timer) : Free-Running Timer instructions
This bit is used to instruct free-run operation. It is effective in both normal mode/overflow mode.
After the interrupt is generated by the end value of the counter, the count is restarted from 0 automatically
when this bit is made effective in the normal mode.
After the interrupt is generated by the counter overflow, the count is restarted from 0(TPUTCN1n.PL=0) or
ECPL[23:0] (TPUTCN1n.PL=1) automatically when this bit is made effective in the overflow mode.
FRT
Free-run
0
Free-run invalid
1
Free-run valid
[bit2] TMOD (TPU Mode) : TPU operation mode
This bit is used to specify TPU operation mode. In the operation mode of the timer, there is the normal
mode that increment the count from 0 to ECPL 23:0, or there is the overflow mode that the count is started
from 0(TPUTCN1n.PL=0) or ECPL[23:0] (TPUTCN1n.PL=1) and the overflow of the counter is detected.
TMOD
Timer Operation Mode
0
Normal mode
1
Overflow mode
MB91520 Series
MN705-00010-1v0-E
2185