Fujitsu FR81S User Manual
APPENDIX
A. I/O Map
FUJITSU SEMICONDUCTOR LIMITED
APPENDIX
FUJITSU SEMICONDUCTOR CONFIDENTIAL
34
Address
Address offset value / Register name
Block
+0
+1
+2
+3
0017A0
H
SCR2/(IBCR2)[R/W]
B,H,W
0--00000
SMR2[R/W] B,H,W
000-00-0
SSR2[R/W] B,H,W
0-000011
ESCR2/(IBSR2)[R/W]
B,H,W
00000000
Multi-UART2
*1 Byte access is
possible only for
access to lower 8
bits.
*2 Reserved
because I
2
C mode
is not set
immediately after
reset.
*3 Reserved
because CSIO
mode is not set
immediately after
reset.
*4 Reserved
because LIN2.1
mode is not set
immediately after
reset.
0017A4
H
― /(RDR12/(TDR12))[R/W] H,W
-------- -------- *3
RDR02/(TDR02)[R/W] B,H,W
-------0 00000000 *1
0017A8
H
SACSR2[R/W] B,H,W
0----000 00000000
STMR2[R] B,H,W
00000000 00000000
0017AC
H
STMCR2[R/W] B,H,W
00000000 00000000
― /(SCSCR2/SFUR2)[R/W] B,H,W
-------- -------- *3 *4
0017B0
H
― /(SCSTR32)/
(LAMSR2)
[R/W] B,H,W
-------- *3
― /(SCSTR22)/
(LAMCR2)
[R/W] B,H,W
-------- *3
― /(SCSTR12)/
(SFLR12)
[R/W] B,H,W
-------- *3
― /(SCSTR02)/
(SFLR02)
[R/W] B,H,W
-------- *3
0017B4
H
―
― /(SCSFR22)
[R/W] B,H,W
-------- *3
― /(SCSFR12)
[R/W] B,H,W
-------- *3
― /(SCSFR02)
[R/W] B,H,W
-------- *3
0017B8
H
―/(TBYTE32)/
(LAMESR2)
[R/W] B,H,W
-------- *3
―/(TBYTE22)/
(LAMERT2)
[R/W] B,H,W
-------- *3
―/(TBYTE12)/
(LAMIER2)
[R/W] B,H,W
-------- *3
TBYTE02/(LAMRID2)
/
(LAMTID2)
[R/W] B,H,W
00000000
0017BC
H
BGR2[R/W] H, W
00000000 00000000
― /(ISMK2)[R/W]
B,H,W
-------- *2
― /(ISBA2)[R/W]
B,H,W
-------- *2
0017C0
H
FCR12[R/W]
B,H,W
---00100
FCR02[R/W]
B,H,W
-0000000
FBYTE2[R/W] B,H,W
00000000 00000000
0017C4
H
FTICR2[R/W] B,H,W
00000000 00000000
―
―
MB91520 Series
MN705-00010-1v0-E
2244